11-03-2020 12:19 PM - edited 11-03-2020 01:42 PM
I just switched from Vivado 2018.3/SDK (licensed) to Vivado 2020.1/Vitis (webpack) to try to learn the workflow of the new tools.
I successfully compiled and exported a previously working Vivado2018.3/SDK Artix-7 project from the new Vivado 2020.1, but I cannot get the simple "Hello, World" application to work in Vitis.
I used the following steps to export:
(1) File->Export->Export Hardware : Platform Type "Fixed", Output "Include bitstream", gave it a name "AVM6C_03" and hit finish. The .xsa file was created successfully in the directory of the Vivado project.
(2) Tools->Launch Vitis IDE: named the workspace "D:\XD\Vitis", and Vitis starts up properly.
(3) In the Vitis shell: Project->Create Application Project-> Create a new platform from hardwware (XSA), browse to the previously created .xsa file, gave it a platform name "AVM6C_03", Generate boot components checkbox checked, clicked Next.
(4) Application Project Details: Gave it a name, clicked Next
(5) Domain: accepted default names, clicked Next
(6) Templates: selected "Hello World", then clicked "Finish". I get an error message saying "Failed to create application project. Please check the Vitis log for details".
(7) Vitis log:
14:55:13 DEBUG : Registering SDKStatusHandler to handle trace exceptions.
14:55:13 DEBUG : Registered the core plugin as the backup plugin for storing repository paths.
14:55:13 INFO : Launching XSCT server: xsct.bat -n -interactive D:\XD\Vitis\temp_xsdb_launch_script.tcl
14:55:13 INFO : Registering command handlers for Vitis TCF services
14:55:16 INFO : XSCT server has started successfully.
14:55:16 INFO : Successfully done setting XSCT server connection channel
14:55:16 INFO : plnx-install-location is set to ''
14:55:16 INFO : Successfully done setting workspace for the tool.
14:55:16 INFO : Successfully done query RDI_DATADIR
14:55:17 INFO : Platform repository initialization has completed.
14:59:47 INFO : Result from executing command 'getProjects': AVM6C_03
14:59:47 INFO : Result from executing command 'getPlatforms':
14:59:49 INFO : Platform 'AVM6C_03' is added to custom repositories.
14:59:50 ERROR :
org.eclipse.core.runtime.CoreException: CDT Project already configured
at org.eclipse.cdt.internal.core.settings.model.ExceptionFactory.createCoreException(ExceptionFactory.java:26)
at org.eclipse.cdt.core.CCorePlugin.mapCProjectOwner(CCorePlugin.java:890)
at org.eclipse.cdt.core.CCorePlugin$1.run(CCorePlugin.java:945)
at org.eclipse.core.internal.resources.Workspace.run(Workspace.java:2289)
at org.eclipse.cdt.core.CCorePlugin.createCProject(CCorePlugin.java:930)
at com.xilinx.sdx.sdk.core.gen.AppCreationHandler.createCProject(AppCreationHandler.java:92)
at com.xilinx.sdx.sdk.core.gen.StandaloneProjectHandler.createCoreApp(StandaloneProjectHandler.java:67)
at com.xilinx.sdx.sdk.core.gen.AppCreationHandler.createApplication(AppCreationHandler.java:79)
at com.xilinx.sdx.sdk.core.gen.AppCreationHandler.execute(AppCreationHandler.java:69)
14:59:51 ERROR : Failed to create application project
org.eclipse.core.runtime.CoreException: CDT Project already configured
at com.xilinx.sdx.sdk.core.gen.StandaloneProjectHandler.createCoreApp(StandaloneProjectHandler.java:150)
at com.xilinx.sdx.sdk.core.gen.AppCreationHandler.createApplication(AppCreationHandler.java:79)
at com.xilinx.sdx.sdk.core.gen.AppCreationHandler.execute(AppCreationHandler.java:69)
at com.xilinx.sdx.sdk.core.SdkAppCreationHandler.executeInternal(SdkAppCreationHandler.java:75)
at com.xilinx.sdx.sdk.core.SdkAppCreationHandler.lambda$1(SdkAppCreationHandler.java:67)
at org.eclipse.core.internal.resources.Workspace.run(Workspace.java:2289)
at org.eclipse.core.internal.resources.Workspace.run(Workspace.java:2311)
at com.xilinx.sdx.sdk.core.SdkAppCreationHandler.execute(SdkAppCreationHandler.java:66)
at com.xilinx.sdx.npw.NewProjectCreationHandler.createApplicationProject(NewProjectCreationHandler.java:232)
14:59:51 ERROR : An unexpected exception occurred in the module 'reading platform'
I then tried to make a new application again:
(1) Select File->New->Application project, go through the steps again to create "Hello, World" and get a popup saying "Platform invalid", with two options, "Add platform to repository" or "Change referred platform".
I then closed Vitis, went back to Vivado and launch Vitis again. The Vitis shell comes up and and make a new "Hello, World" application I named "test". It works this time, and generates the application.
I select Project->Clean all, start build immediately, entire project and it fails with
"fatal error: xil_printf.h:No such file or directory..."
"fatal error: xparameters.h: No such file or directory..."
Vitis log:
15:09:55 DEBUG : Registering SDKStatusHandler to handle trace exceptions.
15:09:55 DEBUG : Registered the core plugin as the backup plugin for storing repository paths.
15:09:55 INFO : Launching XSCT server: xsct.bat -n -interactive D:\XD\Vitis\temp_xsdb_launch_script.tcl
15:09:56 INFO : Registering command handlers for Vitis TCF services
15:09:58 INFO : XSCT server has started successfully.
15:09:58 INFO : plnx-install-location is set to ''
15:09:58 INFO : Successfully done setting XSCT server connection channel
15:09:58 INFO : Successfully done query RDI_DATADIR
15:09:58 INFO : Successfully done setting workspace for the tool.
15:09:59 INFO : Platform repository initialization has completed.
15:10:39 INFO : Result from executing command 'getProjects': AVM6C_03
15:10:39 INFO : Result from executing command 'getPlatforms':
15:10:41 INFO : Platform 'AVM6C_03' is added to custom repositories.
15:10:45 INFO : Platform 'AVM6C_03' is added to custom repositories.
15:15:28 INFO : Checking for BSP changes to sync application flags for project 'test'...
15:15:28 ERROR : Failed to openhw "D:/XD/Vitis/AVM6C_03/export/AVM6C_03/hw/AVM6C_03.xsa"
Reason: ERROR: [Common 17-39] 'hsi::open_hw_design' failed due to earlier errors.
15:15:28 ERROR : Failed to update application flags from BSP for 'test'. Reason: null
java.lang.NullPointerException
at com.xilinx.sdx.sw.internal.SDxSwPlatform.<init>(SDxSwPlatform.java:302)
at com.xilinx.sdx.sw.internal.SDxSwPlatform.create(SDxSwPlatform.java:211)
at com.xilinx.sdx.sdk.core.util.SdkPlatformHelper.getSwPlatform(SdkPlatformHelper.java:60)
at com.xilinx.sdx.sdk.core.build.SdkMakefileGenerationListener.getSwPlatform(SdkMakefileGenerationListener.java:160)
at com.xilinx.sdx.sdk.core.build.SdkMakefileGenerationListener.syncAppFlags(SdkMakefileGenerationListener.java:78)
at com.xilinx.sdx.sdk.core.build.SdkMakefileGenerationListener.preMakefileGeneration(SdkMakefileGenerationListener.java:48)
at com.xilinx.sdk.managedbuilder.XilinxGnuMakefileGenerator.notifyPreMakefileGenerationListeners(XilinxGnuMakefileGenerator.java:91)
at com.xilinx.sdk.managedbuilder.XilinxGnuMakefileGenerator.regenerateMakefiles(XilinxGnuMakefileGenerator.java:75)
at org.eclipse.cdt.managedbuilder.internal.core.CommonBuilder.performMakefileGeneration(CommonBuilder.java:1006)
15:16:38 INFO : Checking for BSP changes to sync application flags for project 'test'...
15:16:38 ERROR : Failed to openhw "D:/XD/Vitis/AVM6C_03/export/AVM6C_03/hw/AVM6C_03.xsa"
Reason: ERROR: [Common 17-39] 'hsi::open_hw_design' failed due to earlier errors.
15:16:38 ERROR : Failed to update application flags from BSP for 'test'. Reason: null
java.lang.NullPointerException
at com.xilinx.sdx.sw.internal.SDxSwPlatform.<init>(SDxSwPlatform.java:302)
at com.xilinx.sdx.sw.internal.SDxSwPlatform.create(SDxSwPlatform.java:211)
at com.xilinx.sdx.sdk.core.util.SdkPlatformHelper.getSwPlatform(SdkPlatformHelper.java:60)
at com.xilinx.sdx.sdk.core.build.SdkMakefileGenerationListener.getSwPlatform(SdkMakefileGenerationListener.java:160)
at com.xilinx.sdx.sdk.core.build.SdkMakefileGenerationListener.syncAppFlags(SdkMakefileGenerationListener.java:78)
at com.xilinx.sdx.sdk.core.build.SdkMakefileGenerationListener.preMakefileGeneration(SdkMakefileGenerationListener.java:48)
at com.xilinx.sdk.managedbuilder.XilinxGnuMakefileGenerator.notifyPreMakefileGenerationListeners(XilinxGnuMakefileGenerator.java:91)
at com.xilinx.sdk.managedbuilder.XilinxGnuMakefileGenerator.regenerateMakefiles(XilinxGnuMakefileGenerator.java:75)
at org.eclipse.cdt.managedbuilder.internal.core.CommonBuilder.performMakefileGeneration(CommonBuilder.java:1006)
15:16:39 ERROR : Failed to compute checksum of hardware specification file used by project 'test'
15:16:39 ERROR : Failed to openhw "D:/XD/Vitis/AVM6C_03/export/AVM6C_03/hw/AVM6C_03.xsa"
Reason: ERROR: [Common 17-39] 'hsi::open_hw_design' failed due to earlier errors.
15:16:39 ERROR : Failed to openhw "D:/XD/Vitis/AVM6C_03/export/AVM6C_03/hw/AVM6C_03.xsa"
Reason: ERROR: [Common 17-39] 'hsi::open_hw_design' failed due to earlier errors.
15:16:39 ERROR : Failed to openhw "D:/XD/Vitis/AVM6C_03/export/AVM6C_03/hw/AVM6C_03.xsa"
Reason: ERROR: [Common 17-39] 'hsi::open_hw_design' failed due to earlier errors.
What am I doing wrong? Is there a tutorial somewhere for non-Zynq standalone MicroBlaze applications?
11-04-2020 07:56 AM
Update: I started from scratch and made a simple MicroBlaze + UART only project, and was able to successfully compile and run the "Hello, World" project, so it looks like my implementation flow was correct.
Perhaps Vitis doesn't work well with large projects ported from 2018.3? I'll try rebuilding it piece-by-piece and see if anything stops working, might be one of my custom IPs or something that wasn't compatible when it did the IP upgrade.
11-04-2020 03:21 PM
Hi @reaiken
Possibly try "reset_project" from Vivado after migrating to 2020.1. This should remove all generated files, in case there is a stale source from 2018.3. Also, I would suggest making sure that the IPs are upgraded to the newest version.
11-06-2020 02:09 PM
Apparently, one of my custom 2018.3 XLS IP blocks is causing all the problems.
If I make an entirely new project and use that XLS IP in the Vivado block, I get all sorts of strange errors in the Vitis IDE, such as not being able to find xil_printf.h or any other Xilinx headers. If I remove that one HLS IP, the program compiles fine with no header errors.
I removed that HLS IP from the original large project and everything works in it now as well.
I'm going to try to recompile the custom IP using Vitis HLS and see if that fixes the issue.
11-07-2020 03:00 PM - edited 11-08-2020 08:34 AM
I compiled my HLS IP under Vitis HLS 2020.1, but I ran into some odd errors with the HLS INTERFACE m_axi pragma.
I had it bundled with an axi-lite port that seemed to work fine under HLS 2018.3, but it flagged a "bundle name" error in Vitis HLS. I just let it create two ports and exported the IP.
After adding the Vitis HLS IP into the project, I get the same compile errors I got with the 2018.3 IP. I tried making a new Vitis "Hello, World" project using the xsa file, but I get the same header errors.
Apparently, my custom HLS IP breaks the xsa and Vitis can't read it. Everything works fine without that custom IP. I unzipped the new xsa and I see the driver for my new IP, and I see it listed in the board support package. I had originally forgotten to add the SW repository to point to the HLS IP, but I fixed that and get the same errors.
I get this warning when I compile:
Invalid project path: Include path not found (D:\XD\Vitis\AVM6C_03_wrapper\export\AVM6C_03_wrapper\sw\AVM6C_03_wrapper\domain_microblaze_0\bspinclude\include).
I get the following errors in the Vitis log:
18:32:16 DEBUG : Registering SDKStatusHandler to handle trace exceptions.
18:32:16 DEBUG : Registered the core plugin as the backup plugin for storing repository paths.
18:32:16 INFO : Launching XSCT server: xsct.bat -n -interactive D:\XD\Vitis\temp_xsdb_launch_script.tcl
18:32:16 INFO : Registering command handlers for Vitis TCF services
18:32:19 INFO : XSCT server has started successfully.
18:32:19 INFO : plnx-install-location is set to ''
18:32:19 INFO : Successfully done setting XSCT server connection channel
18:32:19 INFO : Successfully done query RDI_DATADIR
18:32:19 INFO : Restoring global repository preferences:
D:\XD\IPx\drivers
18:32:19 INFO : Successfully done setting workspace for the tool.
18:32:19 INFO : Platform repository initialization has completed.
18:33:20 INFO : Result from executing command 'getProjects': AVM6C_03_wrapper
18:33:20 INFO : Result from executing command 'getPlatforms':
18:33:21 INFO : Platform 'AVM6C_03_wrapper' is added to custom repositories.
18:33:25 INFO : Platform 'AVM6C_03_wrapper' is added to custom repositories.
18:33:55 INFO : Checking for BSP changes to sync application flags for project 'AVM6C_03'...
18:33:55 ERROR : Failed to openhw "D:/XD/Vitis/AVM6C_03_wrapper/export/AVM6C_03_wrapper/hw/AVM6C_03_wrapper.xsa"
Reason: ERROR: [Common 17-39] 'hsi::open_hw_design' failed due to earlier errors.
18:33:55 ERROR : Failed to update application flags from BSP for 'AVM6C_03'. Reason: null
java.lang.NullPointerException
at com.xilinx.sdx.sw.internal.SDxSwPlatform.<init>(SDxSwPlatform.java:302)
at com.xilinx.sdx.sw.internal.SDxSwPlatform.create(SDxSwPlatform.java:211)
at com.xilinx.sdx.sdk.core.util.SdkPlatformHelper.getSwPlatform(SdkPlatformHelper.java:60)
at com.xilinx.sdx.sdk.core.build.SdkMakefileGenerationListener.getSwPlatform(SdkMakefileGenerationListener.java:160)
at com.xilinx.sdx.sdk.core.build.SdkMakefileGenerationListener.syncAppFlags(SdkMakefileGenerationListener.java:78)
at com.xilinx.sdx.sdk.core.build.SdkMakefileGenerationListener.preMakefileGeneration(SdkMakefileGenerationListener.java:48)
at com.xilinx.sdk.managedbuilder.XilinxGnuMakefileGenerator.notifyPreMakefileGenerationListeners(XilinxGnuMakefileGenerator.java:91)
at com.xilinx.sdk.managedbuilder.XilinxGnuMakefileGenerator.regenerateMakefiles(XilinxGnuMakefileGenerator.java:75)
at org.eclipse.cdt.managedbuilder.internal.core.CommonBuilder.performMakefileGeneration(CommonBuilder.java:1006)
11-19-2020 12:46 AM - edited 11-19-2020 12:49 AM
Hi,
I have the same issue. When I am using only the ZYNQ7 processing system in my block design after exporting and switching to Vitis, the Hello World builds correctly. But if I add a custom IP (made in Vitis HLS 2020.1), after exporting Vitis can not compile the Hello World, can not find xil_printf.h and xparameters.h.
Currently I am using PYNQ-z2. The custom IP just returns the input int variable immediately and has s_axilite interface for input and return.
Errors after compiling:
fatal error: xil_printf.h: No such file or directory helloworld.c /return_input_app/src line 50 C/C++ Problem
fatal error: xparameters.h: No such file or directory platform.c /return_input_app/src line 33 C/C++ Problem
make: *** [Makefile:30: ps7_cortexa9_0/libsrc/return_input_v1_0/src/make.libs] Error 2 return_input C/C++ Problem
make: *** [Makefile:30: zynq_fsbl_bsp/ps7_cortexa9_0/lib/libxil.a] Error 2 return_input C/C++ Problem
make[1]: *** [Makefile:24: libs] Error 1 return_input C/C++ Problem
make[1]: *** [Makefile:30: ps7_cortexa9_0/libsrc/return_input_v1_0/src/make.libs] Error 2 return_input C/C++ Problem
make[2]: *** [Makefile:24: libs] Error 1 return_input C/C++ Problem
Warning after compiling:
Invalid project path: Include path not found (D:\OtthoniProjektek\FPGA\return_input\Vitis\return_input\export\return_input\sw\return_input\standalone_domain\bspinclude\include). return_input_app pathentry Path Entry Problem
Vitis log:
09:30:09 DEBUG : Registering SDKStatusHandler to handle trace exceptions.
09:30:09 DEBUG : Registered the core plugin as the backup plugin for storing repository paths.
09:30:09 INFO : Launching XSCT server: xsct.bat -n -interactive D:\OtthoniProjektek\FPGA\return_input\Vitis\temp_xsdb_launch_script.tcl
09:30:10 INFO : Registering command handlers for Vitis TCF services
09:30:12 INFO : XSCT server has started successfully.
09:30:12 INFO : Successfully done setting XSCT server connection channel
09:30:12 INFO : plnx-install-location is set to ''
09:30:12 INFO : Platform repository initialization has completed.
09:30:12 INFO : Successfully done setting workspace for the tool.
09:30:12 INFO : Successfully done query RDI_DATADIR
09:31:31 INFO : Result from executing command 'getProjects': return_input
09:31:31 INFO : Result from executing command 'getPlatforms':
09:32:51 INFO : Checking for BSP changes to sync application flags for project 'return_input_app'...
09:32:51 ERROR : Failed to openhw "D:/OtthoniProjektek/FPGA/return_input/Vitis/return_input/export/return_input/hw/return_input_v2.xsa"
Reason: ERROR: [Common 17-39] 'hsi::open_hw_design' failed due to earlier errors.
09:32:51 ERROR : Failed to update application flags from BSP for 'return_input_app'. Reason: null
java.lang.NullPointerException
at com.xilinx.sdx.sw.internal.SDxSwPlatform.<init>(SDxSwPlatform.java:302)
at com.xilinx.sdx.sw.internal.SDxSwPlatform.create(SDxSwPlatform.java:211)
at com.xilinx.sdx.sdk.core.util.SdkPlatformHelper.getSwPlatform(SdkPlatformHelper.java:60)
at com.xilinx.sdx.sdk.core.build.SdkMakefileGenerationListener.getSwPlatform(SdkMakefileGenerationListener.java:160)
at com.xilinx.sdx.sdk.core.build.SdkMakefileGenerationListener.syncAppFlags(SdkMakefileGenerationListener.java:78)
at com.xilinx.sdx.sdk.core.build.SdkMakefileGenerationListener.preMakefileGeneration(SdkMakefileGenerationListener.java:48)
at com.xilinx.sdk.managedbuilder.XilinxGnuMakefileGenerator.notifyPreMakefileGenerationListeners(XilinxGnuMakefileGenerator.java:91)
at com.xilinx.sdk.managedbuilder.XilinxGnuMakefileGenerator.regenerateMakefiles(XilinxGnuMakefileGenerator.java:75)
at org.eclipse.cdt.managedbuilder.internal.core.CommonBuilder.performMakefileGeneration(CommonBuilder.java:1006)
11-19-2020 01:50 AM - edited 11-19-2020 01:52 AM
Hi,
I have the same issue. When I'm only ZYNQ7 Processing System block alone in Vivado after exporting the hardware and creating platform and application project based on the xsa file, the Hello World is compiling well. After I add my custom IP (exported and made in Vitis HLS) compilation fails with the following errors:
Description Resource Path Location Type
fatal error: xil_printf.h: No such file or directory helloworld.c /return_input_app/src line 50 C/C++ Problem
fatal error: xparameters.h: No such file or directory platform.c /return_input_app/src line 33 C/C++ Problem
make: *** [Makefile:30: ps7_cortexa9_0/libsrc/return_input_v1_0/src/make.libs] Error 2 return_input C/C++ Problem
make: *** [Makefile:30: zynq_fsbl_bsp/ps7_cortexa9_0/lib/libxil.a] Error 2 return_input C/C++ Problem
make[1]: *** [Makefile:24: libs] Error 1 return_input C/C++ Problem
make[1]: *** [Makefile:30: ps7_cortexa9_0/libsrc/return_input_v1_0/src/make.libs] Error 2 return_input C/C++ Problem
make[2]: *** [Makefile:24: libs] Error 1 return_input C/C++ Problem
Invalid project path: Include path not found (D:\OtthoniProjektek\FPGA\return_input\Vitis\return_input\export\return_input\sw\return_input\standalone_domain\bspinclude\include). return_input_app pathentry Path Entry Problem
I am using pynq-z2 and the custom IP just returns the input in parameter and has s_axilite interface.
Vitis log:
09:30:09 DEBUG : Registering SDKStatusHandler to handle trace exceptions.
09:30:09 DEBUG : Registered the core plugin as the backup plugin for storing repository paths.
09:30:09 INFO : Launching XSCT server: xsct.bat -n -interactive D:\OtthoniProjektek\FPGA\return_input\Vitis\temp_xsdb_launch_script.tcl
09:30:10 INFO : Registering command handlers for Vitis TCF services
09:30:12 INFO : XSCT server has started successfully.
09:30:12 INFO : Successfully done setting XSCT server connection channel
09:30:12 INFO : plnx-install-location is set to ''
09:30:12 INFO : Platform repository initialization has completed.
09:30:12 INFO : Successfully done setting workspace for the tool.
09:30:12 INFO : Successfully done query RDI_DATADIR
09:31:31 INFO : Result from executing command 'getProjects': return_input
09:31:31 INFO : Result from executing command 'getPlatforms':
09:32:51 INFO : Checking for BSP changes to sync application flags for project 'return_input_app'...
09:32:51 ERROR : Failed to openhw "D:/OtthoniProjektek/FPGA/return_input/Vitis/return_input/export/return_input/hw/return_input_v2.xsa"
Reason: ERROR: [Common 17-39] 'hsi::open_hw_design' failed due to earlier errors.
09:32:51 ERROR : Failed to update application flags from BSP for 'return_input_app'. Reason: null
java.lang.NullPointerException
at com.xilinx.sdx.sw.internal.SDxSwPlatform.<init>(SDxSwPlatform.java:302)
at com.xilinx.sdx.sw.internal.SDxSwPlatform.create(SDxSwPlatform.java:211)
at com.xilinx.sdx.sdk.core.util.SdkPlatformHelper.getSwPlatform(SdkPlatformHelper.java:60)
at com.xilinx.sdx.sdk.core.build.SdkMakefileGenerationListener.getSwPlatform(SdkMakefileGenerationListener.java:160)
at com.xilinx.sdx.sdk.core.build.SdkMakefileGenerationListener.syncAppFlags(SdkMakefileGenerationListener.java:78)
at com.xilinx.sdx.sdk.core.build.SdkMakefileGenerationListener.preMakefileGeneration(SdkMakefileGenerationListener.java:48)
at com.xilinx.sdk.managedbuilder.XilinxGnuMakefileGenerator.notifyPreMakefileGenerationListeners(XilinxGnuMakefileGenerator.java:91)
at com.xilinx.sdk.managedbuilder.XilinxGnuMakefileGenerator.regenerateMakefiles(XilinxGnuMakefileGenerator.java:75)
at org.eclipse.cdt.managedbuilder.internal.core.CommonBuilder.performMakefileGeneration(CommonBuilder.java:1006)
11-23-2020 01:45 AM
Update:
Custom IP without saxi_lit interfaces works well in Vitis. So for me the axi interface in my custom IP breaks Vitis...
11-23-2020 02:51 AM
Hello guys,
check this one
https://forums.xilinx.com/t5/Xilinx-IP-Catalog/Fatal-Error-xil-printf-h-xil-types-h-and-xparameters-h-not-found/td-p/1169773
Regards
Pavan
11-23-2020 01:19 PM
01-10-2021 04:10 AM
So, was the issue solved?
Because i'm having the same problem. Can't make Vitis SDK to compile with Vitis HLS block (with axi) included in the vivado project.
Or should i go back to 2019.1 ?
01-10-2021 09:34 AM
I solved it by switching back to 2018.3, it seems to be the only stable version that works with my custom IP with AXI interfaces.