01-13-2021 10:07 AM
In https://www.xilinx.com/support/answers/75527.html referred to https://forums.xilinx.com/t5/High-Level-Synthesis-HLS/Create-IP-AXI4-Lite/td-p/1139280 there is a solution by replacing code in makefile file in custom_ip driver. (It is referred to a custom IP build in Vivado HLS)
I have a basic Vivado 2020.2 project (Microzed 7020 board) with a AXI_Lite peripheral IP without adding any code. Vitis gives error when building the platform. Without this custom IP is OK.
I have been trying replacing the code in makefile but doesn't work.
I hope somebody can help me to find a solution to this issue..
01-14-2021 07:12 AM
Unfortunately, after buliding the platform succesfully.
Running the simple helloworld app the execution fails.
Looking at BSP settings after changing the makefiles I notice the stdin, stdout has changed from default uart1 to uart0.
Any suggestion would be appreciated
01-14-2021 07:26 AM
Steps to get through it:
1 create platform 2 Change if need the BSP settings from UART0 to UART1 3 Replace makefiles of the custom IP
4 Create App 5 Build the whole system 6 Run as hardware: Hello world is working now