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Adventurer
Adventurer
4,224 Views
Registered: ‎05-24-2013

Vivado 2014.1 WebPack

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Hello,

 

I create a simple Hello World in Vivado 2014.1 WebPack. I can see the output on the console as I am supposed to be. Then I just close and open the SDK 2014.1 and run the same project. However this time, it does not show anything.

 

My question is, what can cause this unstability of one time working and another time not? Is this a bug in the Vivado 2014.1 WebPack? Did someone face a similar issue?

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Adventurer
Adventurer
5,710 Views
Registered: ‎05-24-2013

Re: Vivado 2014.1 WebPack

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The reason for the blank console was the UART clock divider. This is a bug of VIVADO I guess and it occurs when you use WebPack and a custom ZYNQ board. The UART_CLK_CTRL register has a divider field (Bits 13:8). It was set to 18 for some reason.

 

Then the following happened. The IO PLL sends out the clock as 2000 MHz and dividing it by 18, the UART gets the 111,1111 MHz. This should not happen, because the UARTs should get 100 MHz. Because of this mismatch, I could not see anything in the console. So in the init_uart() in platform.c, I made the following fix:

 

 // UART CLK Fix, Check the UG 585 page 1516 for bit positions.
 volatile unsigned int regval;
 regval = 0x1401; // setting clk divider to 20, so that UART clk gets 100 MHz as it should.
 Xil_Out32(0xF8000154, regval);

 

After adding this code, I could see the printouts in the console.

 

So if you are using a custom board with Vivado 2014.1 WebPack and do not get anything displayed in the console, it may be that Vivado exports your design to SDK with faulty UART clock parameters. To understand this, check the UART clock settings register and make sure that the UART Controller gets the correct clock frequency.

 

 

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Xilinx Employee
Xilinx Employee
4,223 Views
Registered: ‎10-24-2013

Re: Vivado 2014.1 WebPack

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Hi,
This might be an intermittent issue. Which OS are you working on?
Thanks,Vijay
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Adventurer
Adventurer
4,221 Views
Registered: ‎05-24-2013

Re: Vivado 2014.1 WebPack

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Hello Vijay,

 

I am working on Windows 7 Professional 64-bit sp1. In ISE 14.7 or in Planahead 14.7, I don't have this issue. It occurs only in Vivado 2014.1 WebPack.

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Xilinx Employee
Xilinx Employee
4,214 Views
Registered: ‎08-01-2008

Re: Vivado 2014.1 WebPack

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this may be usability issue. Please make sure you have not done any modification in your design.

Please refer these FAQ and other document for licensing checks
http://www.xilinx.com/tools/faq.htm

http://www.xilinx.com/support/licensing_solution_center.htm
Thanks and Regards
Balkrishan
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Adventurer
Adventurer
4,207 Views
Registered: ‎05-24-2013

Re: Vivado 2014.1 WebPack

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I did not change anything in my design. The tool also shows that it can retrieve a license for synthesis and for implementation.

 

However after the generation of the bitstream, it says:

"Webtalk report has not been sent to Xilinx. Check your network and proxy settings."

 

Can this be the problem?

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Xilinx Employee
Xilinx Employee
4,205 Views
Registered: ‎08-01-2008

Re: Vivado 2014.1 WebPack

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No this should not the problem . This is optional feature which help Xilinx to collect the data from customers for understanding the tool performance at customer end
Thanks and Regards
Balkrishan
--------------------------------------------------------------------------------------------
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Adventurer
Adventurer
5,711 Views
Registered: ‎05-24-2013

Re: Vivado 2014.1 WebPack

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The reason for the blank console was the UART clock divider. This is a bug of VIVADO I guess and it occurs when you use WebPack and a custom ZYNQ board. The UART_CLK_CTRL register has a divider field (Bits 13:8). It was set to 18 for some reason.

 

Then the following happened. The IO PLL sends out the clock as 2000 MHz and dividing it by 18, the UART gets the 111,1111 MHz. This should not happen, because the UARTs should get 100 MHz. Because of this mismatch, I could not see anything in the console. So in the init_uart() in platform.c, I made the following fix:

 

 // UART CLK Fix, Check the UG 585 page 1516 for bit positions.
 volatile unsigned int regval;
 regval = 0x1401; // setting clk divider to 20, so that UART clk gets 100 MHz as it should.
 Xil_Out32(0xF8000154, regval);

 

After adding this code, I could see the printouts in the console.

 

So if you are using a custom board with Vivado 2014.1 WebPack and do not get anything displayed in the console, it may be that Vivado exports your design to SDK with faulty UART clock parameters. To understand this, check the UART clock settings register and make sure that the UART Controller gets the correct clock frequency.

 

 

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