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jdefields
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Registered: ‎12-02-2014

Vivado 2017.1 / 2017.2: PCIe configuration

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Can someone screenshot (or point to a vivado developers guide) how PCIe should be configured in Vivado for a zynqmp?  ZCU102 example would be fine.

 

I'd like to know what the base settings for PCIe as a 'Root Port' should be.  Default class code is showing up as 0x058000 which is definitely wrong (I believe it should be 0x060400).  And even changing that, I get further but am still having issues during Linux

 

 

Thanks,

 

Justin D.

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jdefields
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Registered: ‎12-02-2014
@hbucher, I've seen that one already, but thanks for assisting. That guide doesn't list Bar0 setup, but I think we have it setup already correctly (at least for our current needs)

I actually resolved our specific issue. HW engineer had inverted polarity buffer going to PEX PCIe switch. I inverted the MIO reset line going to the switch to compensate.

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hbucher
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Registered: ‎03-22-2016

@jdefields Here

https://www.xilinx.com/video/hardware/create-pci-express-design-ultrascale-fpga.html

 

Hope this helps.

 

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jdefields
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@hbucher, That's for a soft PCIE core for the PL. 

 

Zynqmp has a hard PCIE core in the PS section.  I'm looking for the configuration for that.

 

Thanks,

 

Justin D.

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hbucher
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@jdefields

Perhaps this should help

https://www.xilinx.com/support/documentation/application_notes/xapp1289-dma-pcie.pdf

 

vitorian.com --- We do this for fun. Always give kudos. Accept as solution if your question was answered.
I will not answer to personal messages - use the forums instead.
jdefields
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Registered: ‎12-02-2014
@hbucher, I've seen that one already, but thanks for assisting. That guide doesn't list Bar0 setup, but I think we have it setup already correctly (at least for our current needs)

I actually resolved our specific issue. HW engineer had inverted polarity buffer going to PEX PCIe switch. I inverted the MIO reset line going to the switch to compensate.

View solution in original post