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dmilway
Observer
Observer
32,314 Views
Registered: ‎05-29-2008

Vivado - Creating custom bus interfaces for IP

Hi,

 

I am trying to port a large amount of my IP into Vivado and would like to generate IP blocks with a custom bus interface.

 

When customising an IP block with the Interface Wizard you can select the interface type from a pull down menu.

I have a local  bus which I would like to group together as a single interface but it does not match with any of the

interface types available in the pull down menu.

 

Is it possible to generate a custom interface spec or are these to only interfaces available for IP.

 

Regards

 

Dave

 

(Vivado 13.2 on Windows XP and Linux)

 

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16 Replies
achutha
Xilinx Employee
Xilinx Employee
32,295 Views
Registered: ‎07-01-2010

Hi Dave,

You can create a custom IP for sure , but when you say a custom bus interface it generally depends on the interface the other module/IP supports to communicate with your custom IP with you own bus spec.

When you use the IP in vivado it has its fixed bus interface through only which you can interface with that IP.

So you may have to use the bus interface available or you may have to tweak communication between the your own bus and the interface supported by the IP/module.

Regards,
Achutha


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dmilway
Observer
Observer
32,285 Views
Registered: ‎05-29-2008

Achutha,

 

I am currently starting to port a number of IP blocks into vivado so I can use the Zync parts.

These IP blocks have their own bus structures and I have started to create a block to map from the AXI to this private bus

and I would like to be able to connect the system using the single wire bus connections, which is where the idea of a custom bus came from.

I currently do now wish to rewrite these blocks to use the axi bus as I would like to continue to use the same files as I have in our current system.

I am still exploring vivado and I was assuming I would need to supply all the signals for a bus interface to avoid errors.

There is a large number of different interface types to select from in the wizard but I cannot find any documentation for them

Do you know of such a document?

 

Thanks

 

Dave

 

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achutha
Xilinx Employee
Xilinx Employee
32,154 Views
Registered: ‎07-01-2010

Hi Dave,

From the description it looks like you are trying to interconnect IPS in vivado.

I think Vivado Designing IP Subsystem using IP Integrator should help http://www.xilinx.com/support/documentation/sw_manuals/xilinx2013_3/ug994-vivado-ip-subsystems.pdf

Let me know if you are not looking for this.

Regards,
Achutha
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andrea.albano
Contributor
Contributor
32,083 Views
Registered: ‎07-25-2011

Hi,

I found a way to do this.

 

Go to Vivado\2013.3\data\ip\interfaces and copy a similar folder of an interface similar to yours.

Change the name of the folder and of the 2 files inside it to your custom name.

Do the same inside the <interface name>.xml and <interface name>_rtl.xml.

In the <interface name>_rtl.xml  define your interface copying from other interface style.

Go to Vivado\2013.3\data\ip and open vv_index.xml

Look for the similar interface you copied and add the same for your interface.

For example I created an I2S interface and seems to work.

 

interfaces/i2s_v1_0/i2s_rtl.xml

<?xml version="1.0" encoding="UTF-8"?>
<spirit:abstractionDefinition xmlns:xilinx="http://www.xilinx.com" xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance">
  <spirit:vendor>xilinx.com</spirit:vendor>
  <spirit:library>interface</spirit:library>
  <spirit:name>i2s_rtl</spirit:name>
  <spirit:version>1.0</spirit:version>
  <spirit:busType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="i2s" spirit:version="1.0"/>
  <spirit:ports>
    <spirit:port>
      <spirit:logicalName>BCLK</spirit:logicalName>
      <spirit:description>BCLK</spirit:description>
      <spirit:wire>
        <spirit:onMaster>
          <spirit:presence>required</spirit:presence>
          <spirit:width>1</spirit:width>
          <spirit:direction>out</spirit:direction>
        </spirit:onMaster>
        <spirit:onSlave>
          <spirit:presence>required</spirit:presence>
          <spirit:width>1</spirit:width>
          <spirit:direction>in</spirit:direction>
        </spirit:onSlave>
        <spirit:defaultValue>1</spirit:defaultValue>
      </spirit:wire>
    </spirit:port>
    <spirit:port>
      <spirit:logicalName>LRCLK</spirit:logicalName>
      <spirit:description>LRCLK</spirit:description>
      <spirit:wire>
        <spirit:onMaster>
          <spirit:presence>required</spirit:presence>
          <spirit:width>1</spirit:width>
          <spirit:direction>out</spirit:direction>
        </spirit:onMaster>
        <spirit:onSlave>
          <spirit:presence>required</spirit:presence>
          <spirit:width>1</spirit:width>
	  <spirit:direction>in</spirit:direction>
        </spirit:onSlave>
      </spirit:wire>
    </spirit:port>
    <spirit:port>
      <spirit:logicalName>DIN</spirit:logicalName>
      <spirit:description>Data in</spirit:description>
      <spirit:wire>
        <spirit:onMaster>
          <spirit:presence>optional</spirit:presence>
          <spirit:width>1</spirit:width>
          <spirit:direction>in</spirit:direction>
        </spirit:onMaster>
        <spirit:onSlave>
          <spirit:presence>optional</spirit:presence>
          <spirit:width>1</spirit:width>
          <spirit:direction>in</spirit:direction>
        </spirit:onSlave>
      </spirit:wire>
    </spirit:port>
    <spirit:port>
      <spirit:logicalName>DOUT</spirit:logicalName>
      <spirit:description>Data out</spirit:description>
      <spirit:wire>
        <spirit:onMaster>
          <spirit:presence>optional</spirit:presence>
          <spirit:width>1</spirit:width>
          <spirit:direction>out</spirit:direction>
        </spirit:onMaster>
        <spirit:onSlave>
          <spirit:presence>optional</spirit:presence>
          <spirit:width>1</spirit:width>
          <spirit:direction>out</spirit:direction>
        </spirit:onSlave>
      </spirit:wire>
    </spirit:port>
  </spirit:ports>


</spirit:abstractionDefinition>

 interfaces/i2s_v1_0/i2s.xml

<?xml version="1.0" encoding="UTF-8"?>
<spirit:busDefinition xmlns:xilinx="http://www.xilinx.com" xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance">
  <spirit:vendor>xilinx.com</spirit:vendor>
  <spirit:library>interface</spirit:library>
  <spirit:name>i2s</spirit:name>
  <spirit:version>1.0</spirit:version>
  <spirit:directConnection>true</spirit:directConnection>
  <spirit:isAddressable>true</spirit:isAddressable>
  <spirit:maxMasters>1</spirit:maxMasters>
  <spirit:maxSlaves>0</spirit:maxSlaves>
</spirit:busDefinition>

 

In vv_index.xml I added these after the 2 of the IIC bus to be sure.

 

<BUSDEF>
	<VLNV value="xilinx.com:interface:i2s:1.0">
	</VLNV>
	<Description value="I2S controller interface definition">
	</Description>
	<XMLFile value="interfaces/i2s_v1_0/i2s.xml">
	</XMLFile>
</BUSDEF>	

 And

<BUSABS>
	<VLNV value="xilinx.com:interface:i2s_rtl:1.0">
	</VLNV>
	<Description value="">
	</Description>
	<XMLFile value="interfaces/i2s_v1_0/i2s_rtl.xml">
	</XMLFile>
</BUSABS>

 

Let me know if there are some other problems.

Andrea Albano
bdSound srl www.bdsound.com
  
bach.long
Observer
Observer
31,441 Views
Registered: ‎08-23-2012

Is it possible to place these bus definition and bus abstraction definition files somewhere in a user IP repository instead of in the Vivado installation directory?

 

How is one supposed to easily distribute an IP block with a custom bus interface witjout requiring files to be copied into $XILINX_VIVADO/data/ip?

 

 

 

 

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andrea.albano
Contributor
Contributor
31,380 Views
Registered: ‎07-25-2011

As far as I know (and I had a talk with a Xilinx FAE on it), it's not possible now.
Andrea Albano
bdSound srl www.bdsound.com
  
swolf
Xilinx Employee
Xilinx Employee
31,358 Views
Registered: ‎07-09-2013

Xilinx doesn't advise editing the xml directly, and unfortunately the functionality to create/edit interfaces is currently not exposed to users.  It would be good to avoid changing the vv_index.xml file altogether.

 

If you do find yourself with a pair interface files, you can put them in a different directory and add that directory to the set of custom repository directories (just like adding a custom ip.  in TCL set_property IP_REPO_PATHS <directory> [current_fileset] ).

 

The only caveat is that the interface files should not be in a directory below an IP Definition (component.xml) file.

 

 

bach.long
Observer
Observer
31,350 Views
Registered: ‎08-23-2012

Thanks, putting the bus definition / abstraction definition files in a directory in ip_repo_paths worked for me. 

 

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andrea.albano
Contributor
Contributor
31,339 Views
Registered: ‎07-25-2011

That's very interesting....I will try to do it
Andrea Albano
bdSound srl www.bdsound.com
  
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Anonymous
Not applicable
14,602 Views

Thanks for the great and detailed example!

 

More on the IP-XACT (P1685) standard development, used to define these interfaces, can be found at Accelera. The IEEE 1685 Standard is available for free download too.

Tags (1)
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nigg
Observer
Observer
14,219 Views
Registered: ‎11-26-2012

Is there anything new with Vivado 2014.2 so one can define additional interfaces? It seems pretty strange that Xilinx "forgot" to implement such a common idea. How are we supposed to work efficiently with Vivado... Is there an other possibility to pool single lines to one bus. I mean a design gets messy very fast otherwise.

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swolf
Xilinx Employee
Xilinx Employee
14,143 Views
Registered: ‎07-09-2013

 

As you might imagine, XIlinx has internal support for this capability.   If you need access to this, please contact your local FAEas this support is internal.

 

Havng said that, in the up comming 2014.3 release, there will be access for all users to define and use their own custom interfaces.

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j.sils
Newbie
Newbie
14,089 Views
Registered: ‎09-24-2014

Hi,

 

I'm not looking to create a new interface, in the way that you have done below, but am looking for examples of how to setup the pre-defined interfaces in the 'board_part.xml'?

I am currently creating my own 'board_part.xml' file.

I have examples of how to create USART, IIC and clock interfaces which work fine, but haven't been able to define HDMI, GTX or RGMII in a way that the tool will recognise.

 

A clock for example:

 

<interface mode="slave" name="sys_diff_clock_200m" type="xilinx.com:interface:diff_clock_rtl:1.0">
      <port_maps>
        <port_map logical_port="CLK_P" physical_port="200m_clk_p"/>
        <port_map logical_port="CLK_N" physical_port="200m_clk_n"/>
      </port_maps>
      <parameters>
        <parameter name="frequency" value="200000000"/>
      </parameters>
</interface>

<port dir="in" name="200m_clk_p">
      <pins>
        <pin iostandard="LVDS" loc="AD18"/>
      </pins>
    </port>
    <port dir="in" name="200m_clk_n">
      <pins>
        <pin iostandard="LVDS" loc="AD19"/>
      </pins>
 </port>

 

Can anyone help in creating this kind of code for HDMI, RGMII, GTX (I tried to follow the structures defined in xilinx.com:interface:hdmi_rtl:1.0 etc), but they aren't recognised.

 

Cheers in advance

Jack

 

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corwinmikke
Visitor
Visitor
13,728 Views
Registered: ‎06-03-2014

I'm using version 2014.3.1 and I can't find this option, Is this feature supported or I have to wait for the next version?

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bggardner
Observer
Observer
12,169 Views
Registered: ‎03-19-2015

I'm not sure in which version it became available, but it now shows up in 2014.4 under Tools... Create Interface Definition...

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ddworkin2015
Observer
Observer
6,688 Views
Registered: ‎04-16-2018

I am using BLOCK DESIGN 2018.3 and I am trying to build a RTL module that will use a custom interface that can connect to the 10G/25G ethernet subsystem. The xxv_ethernet_0 block design has multiple interfaces in use (axis_tx_0, gt_ref_clk, axis_rx_0, etc) and all of these connect just fine to the elements in the board design.. That is, the axis_tx_0 interface of xxv_ethernet connects to M_AXIS interface of xxv_axis_fifo_0 correctly, etc. I have successfully built a module with a "custom" interface that matches the ctl_rx_0 port of the xxv_ethernet system- but, it will not connect.. This makes sense to me as i've built a custom interface cds.int:user:ctrl_ports:1.0 and even though the signals exactly match those in xilinx.com:display_xxv_ethernet:ctrl_ports:2.0 they are still different interfaces.. The interface i "really" want/need to use is xilinx.com:display_xxv_ethernet:ctrl_ports:2.0 located at /xxv_ethernet_0/ctl_rx_0... for some reason, this interface xml is not being seen by the tool. I've added what I think is the proper syntax within the Verilog module, but yet it is not seen correctly... The interface definition shown for Block Interface Properties on /xxv_ethernet_0/ctl_rx_0 is VLNV xilinx.com:display_xxv_ethernet:ctrl_ports:2.0 The interface definition shown for Block Interface Properties on /CTL_RX4_0/display_xxv_ethernet_ctrl_ports_int is VLNV xilinx:display_xxv_ethernet:ctrl_ports_int_rtl:2.0 The message i see is.. [IP_Flow 19-4976] Interface VLNV not found: 'xilinx.com:display_xxv_ethernet:ctrl_ports:2.0' - Ignoring X_INTERFACE_INFO parameter Here is what I've attempted to code.... `timescale 1fs/1fs (* DowngradeIPIdentifiedWarnings="yes" *) module CTL_RX4 ( (* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME CTLRX4" *) (* X_INTERFACE_INFO = "xilinx.com:display_xxv_ethernet:ctrl_ports:2.0 CTLRX4 ctl_rx_check_preamble_0" *) (* X_INTERFACE_INFO = "xilinx.com:display_xxv_ethernet:ctrl_ports:2.0 CTLRX4 ctl_rx_check_sfd_0" *) (* X_INTERFACE_INFO = "xilinx.com:display_xxv_ethernet:ctrl_ports:2.0 CTLRX4 ctl_rx_custom_preamble_enable_0" *) (* X_INTERFACE_INFO = "xilinx.com:display_xxv_ethernet:ctrl_ports:2.0 CTLRX4 ctl_rx_data_pattern_select_0" *) (* X_INTERFACE_INFO = "xilinx.com:display_xxv_ethernet:ctrl_ports:2.0 CTLRX4 ctl_rx_delete_fcs_0" *) (* X_INTERFACE_INFO = "xilinx.com:display_xxv_ethernet:ctrl_ports:2.0 CTLRX4 ctl_rx_enable_0" *) (* X_INTERFACE_INFO = "xilinx.com:display_xxv_ethernet:ctrl_ports:2.0 CTLRX4 ctl_rx_force_resync_0" *) (* X_INTERFACE_INFO = "xilinx.com:display_xxv_ethernet:ctrl_ports:2.0 CTLRX4 ctl_rx_ignore_fcs_0" *) (* X_INTERFACE_INFO = "xilinx.com:display_xxv_ethernet:ctrl_ports:2.0 CTLRX4 ctl_rx_max_packet_len_0" *) (* X_INTERFACE_INFO = "xilinx.com:display_xxv_ethernet:ctrl_ports:2.0 CTLRX4 ctl_rx_min_packet_len_0" *) (* X_INTERFACE_INFO = "xilinx.com:display_xxv_ethernet:ctrl_ports:2.0 CTLRX4 ctl_rx_process_lfi_0" *) (* X_INTERFACE_INFO = "xilinx.com:display_xxv_ethernet:ctrl_ports:2.0 CTLRX4 ctl_rx_test_pattern_0" *) (* X_INTERFACE_INFO = "xilinx.com:display_xxv_ethernet:ctrl_ports:2.0 CTLRX4 ctl_rx_test_pattern_enable_0" *) output wire ctl_rx_check_preamble_0, output wire ctl_rx_check_sfd_0, output wire ctl_rx_custom_preamble_enable_0, output wire ctl_rx_data_pattern_select_0, output wire ctl_rx_delete_fcs_0, output wire ctl_rx_enable_0, output wire ctl_rx_force_resync_0, output wire ctl_rx_ignore_fcs_0, output wire [14:0] ctl_rx_max_packet_len_0, output wire [7:0] ctl_rx_min_packet_len_0, output wire ctl_rx_process_lfi_0, output wire ctl_rx_test_pattern_0, output wire ctl_rx_test_pattern_enable_0 ); endmodule
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