UPGRADE YOUR BROWSER

We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

cancel
Showing results for 
Search instead for 
Did you mean: 
Highlighted
Visitor gregq
Visitor
191 Views
Registered: ‎04-26-2019

Vivado .MMI file generation bug

I have a Microblaze-based design and I am faced with a wrong .MMI file generation bug..The bug seems to appear when I have exactly two slaves on Local Memory Bus core. There is a similar topic related to Vivado 2016.4 (https://forums.xilinx.com/t5/Embedded-Development-Tools/Wrong-BMM-MMI-file-when-LMB-has-2-slaves/m-p/744895#M41026), but currently I have the problem in Vivado 2018.2 and 2019.1.

The way to reproduce the problem:

1. At first step I create block design based project with Microblaze and basic environment.

test1.png

In Address Editor I have following configuration.test1_mem.png

After generating this design I got correct .mmi file.

<AddressSpace Name="microblaze_0.microblaze_0_local_memory_dlmb_bram_if_cntlr" Begin="0" End="131071">

Generated top hdl module (bd/synth/bd.vhd) contains valid BMM_INFO_ADDRESS_SPACE attribute.

attribute BMM_INFO_ADDRESS_SPACE of dlmb_bram_if_cntlr : label is "byte 0x00000000 32 > bd microblaze_0_local_memory/ilmb_bram";

2. At second step I just add one bundle of lmb bram controller and block memory generator to the second dlmb_v10 slave interface.test2.png

New controller is mapped to 0x1000_0000. test2_mem.pngGenerating block design produces top hdl module which contains following strings:

attribute BMM_INFO_ADDRESS_SPACE of dlmb_bram_if_cntlr : label is "byte 0x00000000 32 > bd microblaze_0_local_memory/ilmb_bram bd microblaze_0_local_memory/dlmb_bram1";

attribute BMM_INFO_ADDRESS_RANGE of lmb_bram_if_cntlr_0 : label is " ";

As it seems to me Vivado missed information about lmb_bram_if_cntrl_0 address mapping and tied dlmb_bram1 to dlmb_bram_if_cntlr. In resulting .MMI file there is an information about just this dlmb_bram_if_cntrl with wrong size declaration. The size is seems to be a sum of microblaze_0_local_memory/ilmb_bram and microblaze_0_local_memory/dlmb_bram1 sizes.

<AddressSpace Name="microblaze_0.microblaze_0_local_memory_dlmb_bram_if_cntlr" Begin="0" End="163839">

3. The most interesting part is that Vivado starts to work properly when I make design more complex. To prove it I add one more lmb bundle to third dlmb_v10 slave interface and configure address mapping for new lmb controller.test3.png

test3_mem.pngIn this case Vivado generates correct hdl top module and correct .mmi file. Generated hdl module contains following attributes:

attribute BMM_INFO_ADDRESS_SPACE of dlmb_bram_if_cntlr : label is "byte 0x00000000 32 > bd microblaze_0_local_memory/ilmb_bram";
attribute BMM_INFO_ADDRESS_RANGE of lmb_bram_if_cntlr_0 : label is " ";
attribute BMM_INFO_ADDRESS_SPACE of lmb_bram_if_cntlr_0 : label is "byte 0x10000000 32 > bd microblaze_0_local_memory/dlmb_bram1";
attribute BMM_INFO_ADDRESS_SPACE of lmb_bram_if_cntlr_1 : label is "byte 0x20000000 32 > bd microblaze_0_local_memory/dlmb_bram2";

MMI file includes valid declarations for all address spaces:

<AddressSpace Name="microblaze_0.microblaze_0_local_memory_dlmb_bram_if_cntlr" Begin="0" End="131071">
<AddressSpace Name="microblaze_0.microblaze_0_local_memory_lmb_bram_if_cntlr_0" Begin="268435456" End="268468223">
<AddressSpace Name="microblaze_0.microblaze_0_local_memory_lmb_bram_if_cntlr_1" Begin="536870912" End="536879103">

I attached three projects and .mmi files for described cases.

P.S. To resolve the problem I can use custom .tcl script to generate proper .mmi. But I think Xilinx should finally fix the bug and make Vivado able to generate valid .mmi at least for such basic case.

0 Kudos