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Registered: ‎06-13-2013

Vivado creating my Own AXI4 IP

Hello Xilinx Community,


I have recently migrated to VIVADO and am targeting a zynq part for my upcoming project.  I am spending time now to get up to speed with the tools.  


I want to create a AXI4 Stream interface with exisiting VHDL source code that I used in my last project.



I have created a simple VHDL module that is a numerically controlled oscillator and outputs a sine wave.


The desing uses the IP block memory generator and stores a quadrant of the sine wave in block ram.  I have a COE file that stores the sine points.  With special handling you traverse through the block rom and output a sine wave.  Simple stufff!


Now what I want to do is output the sine wave in AXI4 stream interface.  The idea is to try and output this sine wave into the AXI4 FFT IP.  Therefore I want to create an AXI4 Stream interface.


Here are my steps:


1. Open Vivado 2014.3 Windows(64)

2. Click on Manage IP and Open IP Location or specify new IP location.

3.  The IP catalog with your own personal IP repository should open.

4.  Click Tools and Create and Package IP.

5. Click next 

6. Click on create a new AXI4 peripheral and click next.

7. Name the IP and fill in the details click next. ( I called my Project Xilinx_help)

8.  Choose Interface type : Stream,  Interface Mode: Master  then click next.  (Note: I left the default name M00_AXIS you can rename but this is an example)

9. In this last window Click on EDIT IP and click finish.

10.  Now two VHDL files are created: Xilinx_help_v1_0.vhd  and Xilinx_help_v1_0_M00_AXIS.vhd

11.  I want to now add all the custom logic to create my numerically controlled oscillaotor (Sine wave).

12.  I added to user ports to the TOP level VHD file.   A signal called  CODE which is an enable signal. Another signal called frameSize which specifies how many points of the SINE wave to output before TLAST is pulsed.   I have added the VHD file to see the TOP level added user ports and then passing these ports to the next M00_AXIS module.

13.  Inside the Xilinx_help_V1_0_M00_AXIS.vhd I add handling for creating my sine wave and the AXI4 stream interface.

The code that VIVADO automatically builds as an example is deleted and I replace it all. (Except for the ports)

See attached VHDL file for the details.

14.  Next I need to add Block memory generator IP to store a quarter of a sine wave.  I click on IP catalog.  I type in the search block memory generator and double click on the IP.

15.  Setting up the Block ROM.  Basic Options:   Interface type: Native,   Memory Type:  Single port ROM  

Click on Port A options:  Port A Width : 12    Port A Depth:  2048       Enable Porty type: Always Enabled  Click off Primitives output register (Dont really need for this example)

Click on Other Options:   Click Load Init File              What I do here is copy and paste the .COE file that i created into directory where your IP project is stored.  For example  C:/XILINX_PROJECTS/ip_repo/Xilinx_help_1.0  

Then once you pasted the .COE file into correct folder i click browse in vivado block memory generator.  Find the .COE file and Click EDIT to see that the proper values are in the COE file (It is just a quarter sine wave storing 1500 samples from 0 to 2047).

Click OK to generate the BLOCK ROM.

The Tools ask you to creat the directory C:/XILINX_PROJECTS/ip_repo/Xilinx_help_1.0/src  Click OK.

16.  A box pops up asking for the following output products to be generated.  Click Generate.  This will run blk_mem_gen0_synth_1 






20.  Once it is implemented properly it is time to simulate the Design to make sure it works as intended.  I create a testbench vhdl file called system_tb.vhd.   Create a simple stimulus to output a sine wave.






I click on File Groups and click Merge changes from File gorups Wizard.  I get 1 critical warning:

[IP_Flow 19-530] File Group 'bd_tcl (Block Diagram)': Component file 'bd/bd.tcl' (c:/sftpro_gen3/ip_repo/edit_Xilinx_help_v1_0.srcs/sources_1/imports/xilinx_help_1.0/bd/bd.tcl) does not exist.


I ignore this warning.


I click on Customization parameters and click merge changes form Customization parameters wizard.


Do the same for the Customization GUI.  


Now it should look like this : IP_GUI.png


Next Click on Review and Package and click RE-Package IP.  Get one Critical warning:   

[IP_Flow 19-1663] Duplicate IP found for 'iders.ca:user:Xilinx_help:1.0'. The one found in IP location 'c:/sftpro_gen3/ip_repo/edit_Xilinx_help_v1_0.srcs/sources_1/imports/xilinx_help_1.0' will take precedence over the same IP in location c:/SFTPRO_GEN3/ip_repo/Xilinx_help_1.0


I am done making my IP.


Now close the project.  The IP should now be in the IP catalog.


22.  Create a new project.  First close the IP repository and click Create New Project

I called it Xilinx_project and using the Zynq 7020   zedboard.  (I made the IP directed at this board as well)


23.   Create new block design .  Left it at default name Design_1


24.  ADD IP to block design.  Notice the IP just created is not in the IP catalog.  To add your IP go to Project settings in the Flow navigator and than click on IP.  Click on ADD repository and add the Folder of where you made the XILINX_HELP IP.



Click ok.


25.  Click Add IP again.  I find my Xilinx_help IP and click add.


This is where the problems begin for me.  The Block does not represent the same block i had before.  The interface Code and Framesize are now missing.  




Ok I will continue.  I add ports and interface to the design.  I save the Block design.  and then   Create VHDL top wrapper.  Pretty standard stuff.


I then synthesize.  It synthesizes.


I then implement and I get a critical warning:


[Project 1-486] Could not resolve non-primitive black box cell 'blk_mem_gen_0' instantiated as 'design_1_i/Xilinx_help_0/U0/Xilinx_help_v1_0_M00_AXIS_inst/sine_wave' [c:/SFTPRO_GEN3/Xilinx_project/Xilinx_project.srcs/sources_1/ipshared/iders.ca/Xilinx_help_v1_0/a2f8fca3/hdl/Xilinx_help_v1_0_M00_AXIS.vhd:67]


My main problems now:

Where did I go wrong?  My interface is missing Code and Framesize and it seems like my block memory generated in my IP cannot be found??   Of course I can't simulate this block design.  


Please help me to figure out what I am doing wrong?   


I have retried this same excercise over and over.  Sometimes I can get the framesize and code to show up on the block design sometimes not.  I have also experienced one time it created Verilog AXI4 files instead of VHD files when I had the IP settings set at VHD.  (That is a bug).  It seems like my block memory generator is lost once i package the IP.  I do not know what is going on.  


Please help this shouldn't be this hard.  


I attached all my IP VHD files.  





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3 Replies
Registered: ‎06-13-2013

Re: Vivado creating my Own AXI4 IP

Steps are missing for some reason:


16. A box pops up asking for the following output products to be generated. Click Generate. This will run blk_mem_gen0_synth_1
17. Now go back into your Xilinx_help_v1_0_M00_AXIS.vhd and call the Block rom component and instantiate it (in VHDL).

COMPONENT blk_mem_gen_0
clka : IN STD_LOGIC;

sine_wave : blk_mem_gen_0
clka => M_AXIS_ACLK,
addra => addr,
douta => sine_out_i

18. Next I right click on Top level module and click Copy all files into Project.

19. I then Run Synthesis and implementation on the design. Click on run implementation in the Flow navigator window. This will do both Synthesis and implementation.

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Registered: ‎06-13-2013

Re: Vivado creating my Own AXI4 IP

Still looking for help on how to use a block ram IP when creating AXI4 IP in vivado.

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Visitor tni
Registered: ‎11-04-2014

Re: Vivado creating my Own AXI4 IP

I am interested in the solution to this post.


I'm trying to build my own AXI IP core and after packaging it,  I've had the same issues simulating the core with my main design. 

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