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tk_stoeber
Observer
Observer
10,097 Views
Registered: ‎12-04-2013

Watching PL addresses in SDK (System Debugger)

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Hello everyone,

on Zynq, I've implemented some custom peripherals in the PL connected to the PS through M_AXI_GP0. The PS can access the PL peripherals using a set of registers.
My peripherals work fine - I can read and write data from/to the registers. So the PL does what it should do and the AXI Interface works correctly.

My problem is:
I want to see the PL Registers when I'm debugging the PS application in SDK (2013.3) but the memory view only shows "????????" for all addresses starting at 0x40000000.
I also tried watching *((unsigned long*)0x40000000) in the Expressions view and got the fault "Exception: Cannot read target memory. PL AXI slave ports access is not allowed"

This must be a problem with SDK and System Debugger (GDB memory view works for the PL addresses but I can't use it because I'm debuging a multicore application).

Do a have to change any settings in SDK od where is the problem?

The person in this post had the same issue:
http://forums.xilinx.com/t5/Embedded-Development-Tools/Exception-Cannot-read-target-memory-PL-AXI-slave-ports-access-is/td-p/369563

Best regards

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sadanan
Xilinx Employee
Xilinx Employee
9,653 Views
Registered: ‎10-21-2010

Hi,

By default debugger blocks access to all PL regions, so the memory window shows '????..'

 

You can tell the debugger to allow accesses to a specific region by adding that region as a memorymap entry. You can do this by selecting the APU target in XSCT console view and running the command memmap -addr <addr> -size <size>. Please note that memory map entries are deleted when you close the debug session, so you may want to script these commands and source the script after launching debug session.

 

In 2017.2, SDK will automatically add all the PL regions to memory map, so this step would not be needed

View solution in original post

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sampatd
Scholar
Scholar
10,090 Views
Registered: ‎09-05-2011
Is your application executing from a memory (BRAM or MIG) that is present in the PL side?

Can you check the linker script settings of your application?

If it is, please try modifying the linker script so that the application executes from either PS DDR memory or PS OCM RAM (if the application is small enough to fit in it).

Also, make sure the stack and heap sections are utilizing the PS ddr.

To edit the linker script in SDK, please refer to the link below:
http://www.xilinx.com/support/documentation/sw_manuals/xilinx14_7/SDK_Doc/tasks/sdk_t_create_lscript.htm

Let me know if the issue still persists after these changes.
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tk_stoeber
Observer
Observer
10,089 Views
Registered: ‎12-04-2013

Thanks for your answer!

 

My code is executed from DDR. Heap and Stack are in DDR too.

The PL address space is not added to the linker script because I don't have code or data there. I'm not using PS-accessable BRAM.

 

I have user defined HDL Code in the PL which has adress-mapped registers that can be accessed by the PS over an AXI4-Lite Interface.

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sampatd
Scholar
Scholar
10,086 Views
Registered: ‎09-05-2011
Can you attach the archived SDK workspace?
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tk_stoeber
Observer
Observer
10,066 Views
Registered: ‎12-04-2013

Attached you find one of my small singlecore evaluation projects for Zedboard.

I get the same behavior in every project when I want to read PL addresses with the debugger.

 

This specific project uses Standard IP-Cores for GPIOs included in the Vivado IP Catalog. As you see in the code I get the correct values for the buttons and switches on the Board at the addresses  0x41210000 and 0x41200000 but reading these Values with the System Debugger (Expressions or Memory view) doesn't work.

 

-> Exception: Cannot read target memory. PL AXI slave ports access is not allowed

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tk_stoeber
Observer
Observer
9,917 Views
Registered: ‎12-04-2013

Are the no solutions to this problem? Or is it in newer versions of SDK already working?

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jhsetyo
Visitor
Visitor
6,736 Views
Registered: ‎08-01-2013

Any update on this issue? I am using SDK 2017.1, and I am still having the same issue.

I created a custom AXI peripheral that has 2 AXI4 Lite Slave ports.

Slave0 base address is at 0x43c10000

Slave1 base address is at 0x43c11000

 

Using System Debugger Memory view, I could see correct data at 0x43c10000, but the memory view displayed "????????" at 0x43c11000.

 

If I stepped the code that reads from location 0x43c11000, I could read correct data.

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sadanan
Xilinx Employee
Xilinx Employee
9,654 Views
Registered: ‎10-21-2010

Hi,

By default debugger blocks access to all PL regions, so the memory window shows '????..'

 

You can tell the debugger to allow accesses to a specific region by adding that region as a memorymap entry. You can do this by selecting the APU target in XSCT console view and running the command memmap -addr <addr> -size <size>. Please note that memory map entries are deleted when you close the debug session, so you may want to script these commands and source the script after launching debug session.

 

In 2017.2, SDK will automatically add all the PL regions to memory map, so this step would not be needed

View solution in original post

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arevata
Visitor
Visitor
6,436 Views
Registered: ‎03-08-2016

Hi,

 

I'm running VIVADO 2017.2 with the ZCU102 Evaluation and try to dump a block ram located on the PL side, but I still a page from memory windows full of  "??????" and if I try an access with XSCT I get the message "access not allowed".

I have also try the memap command but without success until now.

 

Does it necessary to set  specific options on SDK to access PL address space ? I don't have this problem with ZYNQ 7000 (Zedboard) and VIVADO 2016.4.

 

Philippe

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sadanan
Xilinx Employee
Xilinx Employee
6,431 Views
Registered: ‎10-21-2010

Hi,

 

Before running memmap command for zcu, you may have to select the PSU target. Did you try that

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arevata
Visitor
Visitor
4,065 Views
Registered: ‎03-08-2016

Thanks for your answer. It works fine after selecting  the target 4 (PSU).

 

The 2017.2 version had not to it resolve this problem ?

 

Thanks a lot.

Regards,

 

Philippe

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sadanan
Xilinx Employee
Xilinx Employee
4,058 Views
Registered: ‎10-21-2010

Hi Philippe,

 

AFAIK, 2017.2 should set the memmap for all the PL address ranges. I'll check if that is not the case

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binbinyantai
Observer
Observer
2,659 Views
Registered: ‎09-12-2017

hi :

2017.4 has same problem, i can not watching pl address in sdk's memory window . can i  follow this AR to fix this problem?

AR# 69607 SDK 2017.2 - System Debugger does not have access to PL address regions on Zynq UltraScale+ MPSoC

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chrischan
Contributor
Contributor
2,525 Views
Registered: ‎06-20-2018

I have exactly the same issue with 2018.2, does the same patch(xsct_2017.2_patch.zip) still apply?

xsct% mrd 0xa0000000
Memory read error at 0xA0000000. Access can hang PS interconnect

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chrischan
Contributor
Contributor
2,508 Views
Registered: ‎06-20-2018

 

Got it working with -force option

xsct% memmap -addr 0xa0000000 -size 0x10 -flags 3
xsct% mrd -force 0xa0000000 4
A0000000: 00000001
A0000004: 12345678
A0000008: 00000000
A000000C: 00000000

 

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