cancel
Showing results for 
Search instead for 
Did you mean: 
Highlighted
Observer
Observer
289 Views
Registered: ‎11-08-2017

What are the possible reasons of AXI-Lite wrintings hang?

Jump to solution

Hi community!

My team and I are implementing a simple AXI Lite communication for configuring some custom IP registers. We are using RTEMS real-time OS, in the software part, but we also tested this issue using baremetal code. The issue is that execution hangs after two consecutive writings in AXI register, we use a normal C pointer, nothing complex. After note that, we added a delay between the writings. The execution does not hang now. Why could this happen?

What could be the possible causes of hung execution related to AXI-Lite communication? What should the developers have into account before implementing an AXI communication (PL and PS side)? I've searched about and I found multiple causes (PL side problem, Linux software...) but there is not a page at knowledge base gathering all this. It could be useful.

Thanks in advance!

0 Kudos
1 Solution

Accepted Solutions
Scholar
Scholar
264 Views
Registered: ‎05-21-2015

Re: What are the possible reasons of AXI-Lite wrintings hang?

Jump to solution

@fdpousa,

Vivado's AXI-lite demonstration designs have had bugs in them since at least 2016.  These were reported in late 2018.  Other, similar, bugs were reported in their AXI (full) demonstration design in mid 2019.  I've been told that these bugs will be fixed in the new 2020 Vivado release, but have yet to check such a release to know if they are fixed.

The bugs primarily center around backpressure.  In the presence of any backpressure, the demonstration designs will drop requests.  Here's a trace showing the basic AXI-lite write bug,

axil-xilinx-write-fail.png

The trace ends in a steady state, after two write requests have been made and only one responded to.  This bug was fixed in their demonstration IP some time before 2018.3, although it still lives on in any user code that was built around this IP.

There's a similar read bug in the demo designs as well, shown below.

axil-xilinx-read-fail.png

As with the write bug, the trace ends in a steady state after two read requests have been made but only one was replied to.  This bug has not (yet) been fixed.

Although these IP cores have been simulated for years, the failure of most simulations to check a cores performance in the presence of both forward and backward pressure has led to the bugs.  Instead, these bugs were found through a formal property checker.  The property checker, SymbiYosys, and the properties that caught these bugs are open source and available for download.

If you do a bit of a forum search, you will find that others have had these same problems for years.  If you do an IP search, you will find many of the same bugs living within other Xilinx IP.  You can also find alternate AXI or AXI-lite demonstration IP that doesn't have these bugs, while Xilinx works to update Vivado.  (I'd provide more links, but my forum posts would be marked as spam if I did so ...)

Dan

View solution in original post

4 Replies
Highlighted
Scholar
Scholar
275 Views
Registered: ‎08-07-2014

Re: What are the possible reasons of AXI-Lite wrintings hang?

Jump to solution

@fdpousa,

A function verification (simulation) of your design should show you why stuffs are failing. Have you done that?

Having said that, are you using custom made AXI4-Lite slaves or IP cores?

If you are using your own slaves, make sure thay are fully AXI4-Lite compliant before plugging them in to your design.

What could be the possible causes of hung execution related to AXI-Lite communication?

A deadlock situation b/w a slave and a master possibly...

Difficult to say without more info!

 

--------------------------------------------------------------------------------------------------------
FPGA enthusiast!
All PMs will be ignored
--------------------------------------------------------------------------------------------------------
0 Kudos
Scholar
Scholar
265 Views
Registered: ‎05-21-2015

Re: What are the possible reasons of AXI-Lite wrintings hang?

Jump to solution

@fdpousa,

Vivado's AXI-lite demonstration designs have had bugs in them since at least 2016.  These were reported in late 2018.  Other, similar, bugs were reported in their AXI (full) demonstration design in mid 2019.  I've been told that these bugs will be fixed in the new 2020 Vivado release, but have yet to check such a release to know if they are fixed.

The bugs primarily center around backpressure.  In the presence of any backpressure, the demonstration designs will drop requests.  Here's a trace showing the basic AXI-lite write bug,

axil-xilinx-write-fail.png

The trace ends in a steady state, after two write requests have been made and only one responded to.  This bug was fixed in their demonstration IP some time before 2018.3, although it still lives on in any user code that was built around this IP.

There's a similar read bug in the demo designs as well, shown below.

axil-xilinx-read-fail.png

As with the write bug, the trace ends in a steady state after two read requests have been made but only one was replied to.  This bug has not (yet) been fixed.

Although these IP cores have been simulated for years, the failure of most simulations to check a cores performance in the presence of both forward and backward pressure has led to the bugs.  Instead, these bugs were found through a formal property checker.  The property checker, SymbiYosys, and the properties that caught these bugs are open source and available for download.

If you do a bit of a forum search, you will find that others have had these same problems for years.  If you do an IP search, you will find many of the same bugs living within other Xilinx IP.  You can also find alternate AXI or AXI-lite demonstration IP that doesn't have these bugs, while Xilinx works to update Vivado.  (I'd provide more links, but my forum posts would be marked as spam if I did so ...)

Dan

View solution in original post

Highlighted
Scholar
Scholar
252 Views
Registered: ‎08-07-2014

Re: What are the possible reasons of AXI-Lite wrintings hang?

Jump to solution

@dgisselq,

You must have seen that Xilinx license AXI VIPs as well.

If the Xilinx AXI or AXI4-Lite has bugs it would not be prudent to use their VIPs as well I guess....just a thought.

--------------------------------------------------------------------------------------------------------
FPGA enthusiast!
All PMs will be ignored
--------------------------------------------------------------------------------------------------------
0 Kudos
Highlighted
Scholar
Scholar
247 Views
Registered: ‎05-21-2015

Re: What are the possible reasons of AXI-Lite wrintings hang?

Jump to solution

@dpaul24,

Prudent?  Maybe.

The frustration is that the bugs identified above had all passed the AXI VIP checker.  I found many users claiming their designs worked, and that they passed the VIP checks, only to find these bugs still existing within their designs.  The basic problem is that simulation will only check for the bugs you are expecting and looking for, whereas the formal tool that caught the bugs above does so via an exhaustive search.

I also found it telling to learn that Xilinx does not test their own IP using the AXI VIP.  Even they realize, therefore, the limitations of their own tool.

Will the AXI VIP help to find bugs in a user design?  Possibly.  Will it find all the bugs?  Definitely not.  For that, a formal property checker works much better.

Dan

0 Kudos