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Adventurer
Adventurer
258 Views
Registered: ‎10-12-2018

What does launch on hardware do exactely?

I want to know what tasks done by the launch on hardware function. image.png

I think it make AXI transaction depending on the *.elf and writes the binary program into proper address locations, then it resets the PC (program-counter). Any other tasks?

My current problem is that my zedboard behaves differently at the first execution after the power-up, and the following executions. (Differently: I can catch the interrupt at the first time, but not the second time, however the reset pin of the CPU is still active.) So I think that the power-on reset differs from the reset of launch on hardware function.

What kind of reset is done by the launch on hardware?

How can I reset the CPU without unload the FPGA bitstream? If I force rst command in the XSCT terminal, the PL part becomes unprogrammed.

I use:

  • Vivado, SDK 2017.4
  • Zedboard (xc7z020)
  • Win10
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2 Replies
Adventurer
Adventurer
247 Views
Registered: ‎10-12-2018

Re: What does launch on hardware do exactely?

I have found the solution for my problem under the Run Configuration menu:

image.png

If I check program FPGA the code behaves as expected all the time.

But still I dont know what functions should called for safety init (same behavior) without reprogramming the FPGA.

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Moderator
Moderator
160 Views
Registered: ‎10-06-2016

Re: What does launch on hardware do exactely?

Hi @betontalpfa

As you already figure out the steps executed by the System Debugger when "Running" or "Debugging" into the target are based on the configuration settings defined on the wizard.

There are different checkboxes and each one enables/disables features, so you need to chose the ones required for your specific use case. The explanation box is quite useful as well, i.e. Reset entire system = Reset everything including PL

If you don't want reprogram FPGA you just remove those options from your configuration. However that does not guarantee "same behaviour", I mean you need to take into account that FPGA logic has not been reset so might state in a different condition than after POR.

Finally SDK log windows will show you all the commands issued by the System Debugger for the loading process!

Regards

Ibai


Ibai
Don’t forget to reply, kudo, and accept as solution.
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