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jeffsen
Explorer
Explorer
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Registered: ‎12-11-2007

What is the proper procedure to implement IOBUF for user-ip in EDK?

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Hi, all,

 

I created my own OPB user IP which contains IO signals: my_io_input, my_io_output, my_io_en_b. The problem is how to implement the IOBUF for my IP?

 

Years ago I managed to set my PowerPC system(EDK project) as a sub-module in ISE project and in the ISE top level design, implement IOBUF which instantiates the above IO signals. However I believe this is not wise.

 

I saw somebody created the OPB IP and simply modified the .mpd file to add the IOBUF there. I tried, it works to some extent...  in case I modied the .mpd file before I import my IP to EDK, when I run the import user peripheral to EDK, what I have modified will be discarded and saved in //data_old folder. This should not be normal, is it?

 

Any other official/cleverer solutions?

 

Thanks in advance.

 

regards,
jeffsen

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Chadn_na
Xilinx Employee
Xilinx Employee
7,734 Views
Registered: ‎08-15-2007

There are really two ways to do it

1 - Include the three tristate signals in your pcore (<sig>_O, <sig>_I, <sig>_T) and make these ports on your pcore.  Platgen, utility that creates HDL wrapper files, with instantiate an IOBUF.  In this case you will want to set THREE_STATE in your pcores MPD file to TRUE.  See psf_rm.dpf for more info on this parameter.  Note this is the way the EDK cores handle THREE STATE ports.

2- As you have already described, include the IOBUF in your pcore.  In this instance you will need to set THREE_STATE to false.

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golson
Scholar
Scholar
6,587 Views
Registered: ‎04-07-2008

Hi,

 

I have been waiting to hear someone tell you the correct way to do it.  I do not understand why you can't instantiate a IOBUF Tristate component in your IPIF.

 

I have no tristates in my design.  But I do have Differential Drivers in my design and I was able to instatiate the components into my IPIF.

 

Thanks,

  Gary

 

Message Edited by golson on 09-16-2008 04:32 PM
jeffsen
Explorer
Explorer
6,574 Views
Registered: ‎12-11-2007

Hi, Gary,

 

thanks for your input.

 

Actually one of my colleague did the same as you mentioned. This is less trouble, while I still believe there should be some other way which is even conciser.

 

regards,

Jeffsen

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Chadn_na
Xilinx Employee
Xilinx Employee
7,735 Views
Registered: ‎08-15-2007

There are really two ways to do it

1 - Include the three tristate signals in your pcore (<sig>_O, <sig>_I, <sig>_T) and make these ports on your pcore.  Platgen, utility that creates HDL wrapper files, with instantiate an IOBUF.  In this case you will want to set THREE_STATE in your pcores MPD file to TRUE.  See psf_rm.dpf for more info on this parameter.  Note this is the way the EDK cores handle THREE STATE ports.

2- As you have already described, include the IOBUF in your pcore.  In this instance you will need to set THREE_STATE to false.

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jeffsen
Explorer
Explorer
6,533 Views
Registered: ‎12-11-2007

Hi, Chadn,

 

Thanks!

 

Actually I selected the option 2. In my case, the IO_input should connect with <sig>_o, which is also the output of my own IP, thus it's impossible to integrate the IOBUF in .mpd file, coze IO_input must be also type IN. Thus I designed another IO_interface module which implements the IOBUF and exactly maps the input signal(to this module) signal to IO_input...

 

regards,

jeffsen 

 

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