Whats the proper way to use NGC netlists within an IP core
I've created an OPB peripheral with several registers for reading/writing. I want to use these registers as inputs/outputs from a component that I've instantiated within the user_logic. I created this component in ISE and disabled "Add I/O Buffers" in the synthesis options. The result is an NGC implementation of this component. I then re-imported the OPB peripheral so that it includes this NGC netlist. This appears to work, that is to say the NGC file is loaded as a core in the appropriate places and no steps of the implementation process seem to fail. This overall design undergoes PAR successfully, however the OPB IP doesnt work correctly. I don't think the MAP and PAR steps use my NGC component. The final device usage of a base system is approximately 2000 slices and I know my component uses approximately another 2000 slices. However the final device usage of the system is only around 2500 slices. Any help with this would be greatly appreciated.
There is an example on the FPGA Developer website that should solve your problem. They create a peripheral with the Peripheral Wizard and from within the user logic they instantiate a multiplier core from an NGC netlist file.