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Visitor alexabctech
Visitor
3,153 Views
Registered: ‎10-25-2012

Write Cycle Simulation of AXI4-Lite IPIF Not Functional w/AXI4 Lite Master BFM

When the latest version of the AXI4 Lite IPIF slave interface (axi_lite_ipif_v1_01_a) is used, write_burst initiated waveforms show that the AXI4 Lite Master BFM drives AWVALID = 1.  The write cycle never advances beyond that because the slave logic statemachine inside axi_lite_ipif is waiting for the simultaneous occurrence of AWVALID = 1 and WVALID = 1 from the master.

 

My initial/immediate solution for this problem is simply to reference the previous version (axi_lite_ipif_v1_00_a) of the slave AXI4 Lite IPIF.  This earlier version requires only AWVALID = 1 to proceed with the write_burst transaction.  This can be seen by comparing the slave_attachment.vhd modules in the two versions, specifically line 407 of version axi_lite_ipif_v1_00_a and line 392 of axi_lite_ipif_v1_01_a.

 

After looking into this a bit more thoroughly, I believe that the problem is not in the Xilinx (axi_lite_ipif) library.  In fact, the AXI4 Lite Master BFM appears to not be compliant in regards to the write transaction dependencies paragraph in the AXI specification.  According to the ARM AMBA AXI Protocol (IHI0022E) Specification, in section A3.3.1 Dependencies between channel handshake signals, on page 43, under the Write transaction dependencies paragraph, the second bulleted item states “the slave can wait for AWVALID or WVALID, or both before asserting AWREADY”.

 

Xilinx may want to investigate this issue and determine if an AXI4 Lite Master BFM update is required.

 

I hope this helps someone else.

 

Alex

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2 Replies
Moderator
Moderator
3,128 Views
Registered: ‎08-25-2009

Re: Write Cycle Simulation of AXI4-Lite IPIF Not Functional w/AXI4 Lite Master BFM

With reference to the AMBA AXI protocol specification, it says:

  • the slave can wait for AWVALID or WVALID, or both, before asserting AWREADY
  • the slave can wait for AWVALID or WVALID, or both, before asserting WREADY

 

This implies that the slave does not need to support all of the 3 possible scenarios however the AXI Master BFM will only play the scenario and if the slave does not support it then the simulation will stall.

 

Each scenario is reflected by the function level API:

Scenario 1: Before the slave asserts AWREADY and/or WREADY the slave can wait for AWVALID. This is modeled using the function level API “WRITE_BURST”

Scenario 2: Before the slave asserts AWREADY and/or WREADY the slave can wait for WVALID. This is modeled using the function level API “WRITE_BURST_DATA_FIRST”

Scenario 3: Before the slave asserts AWREADY and/or WREADY the slave can wait for both AWVALID and WVALID. This is modeled using the function level API “WRITE_BURST_CONCURRENT”

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Visitor alexabctech
Visitor
3,106 Views
Registered: ‎10-25-2012

Re: Write Cycle Simulation of AXI4-Lite IPIF Not Functional w/AXI4 Lite Master BFM

You are absolutely correct.  Thanks for your comments.

 

I have been so focused on getting past a problem I had with the AXI BFM licensing that once everything began working (which happened to be while using the write_burst function level API) I forgot about the other write functions.  

 

In any event, the older slave interface (axi_lite_ipif_v1_00_a) works with both the write_burst function and the write_burst_concurrent function, where the newer version (axi_lite_ipif_v1_01_a) works with only write_burst_concurrent.

 

I did not need (and ran out of time) to look into the write_burst_data_first.

 

Alex

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