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florisvandrunen
Observer
Observer
11,780 Views
Registered: ‎09-20-2012

Writing data in AXI register through XIo_Out32(address,data) or Xil_Out32(address,data)

Hello everyone,

 

I'm trying to send data to a register of a custom slave, by using a software accesible register.

I connected the slave to a AXI lite bus and the baseaddress is AXI_lite_slave_BASEADDR.

 

I'm trying to send the following data;

 

XIo_Out32(axi_lite_slave_BASEADDR,0x00000001);

or

Xil_Out32(axi_lite_slave_BASEADDR,0x00000001);

 

But on both command I've got the same problem.

The data gets received by the slave and it does what I want.

 

But the XIo_Out32 and Xil_Out32 function don't get out of the function, so it won't return

and the program freezes.

 

If I'm trying to send data to other addresses which are not in use,

it got sent correctly and the functions return.

 

How to fix this?

 

Thanks in advance,

Best regards,

Floris van Drunen

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16 Replies
dfuschelberger
Adventurer
Adventurer
11,762 Views
Registered: ‎01-02-2012

Hi,

 

try putting "(u32)" in front of your hex value, like this: Xil_Out32((axi_lite_slave_BASEADDR), (u32) (0x00000001));

 

Cheers,

David

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florisvandrunen
Observer
Observer
11,756 Views
Registered: ‎09-20-2012

Thanks for your reaction,
but I tried it and unfortunately this is not the solution.
What could cause the hanging in the XIo_Out32 function?
Am I supposed to write into the axi_lite_slave_BASEADDR?
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dfuschelberger
Adventurer
Adventurer
11,747 Views
Registered: ‎01-02-2012

"XIo_Out32" (in former "xio.h") is discontinued and has been mapped to "Xil_Out32" (in "xil_io.h"), take a look here: http://www.xilinx.com/support/documentation/sw_manuals/xilinx14_2/oslib_rm.pdf

 

Does your custom slave conform to the AXI Specs? It might be that a missing response is causing the function to hang. Is the address of your custom Slave mapped? I suggest you try the same thing with a CIP-created Slave - if it works, you'll need to verify your Slave's functionality.

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florisvandrunen
Observer
Observer
11,741 Views
Registered: ‎09-20-2012

What does my slave have to respond?Yes it is.
I can't create an AXI lite slave, because I'm using Xilinx 12.4, so I can't create AXI peripherals.
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dfuschelberger
Adventurer
Adventurer
11,738 Views
Registered: ‎01-02-2012

Well, if you designed it according to the AXI specs, you should actually know... :-) Even AXI4-Lite has some response signals, please refer to the specs @arm.com to check them out.
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florisvandrunen
Observer
Observer
11,722 Views
Registered: ‎09-20-2012

I need to give back an BValid signal and a BResp signal right?
If I'm doing this the same still occurs.
How to fix this?
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medanouar
Visitor
Visitor
11,407 Views
Registered: ‎07-25-2012

Hi Floris,

 

I'm seeing the same problem as yours and I've got "segmentation fault" error when calling Xil_Out32 and Xil_In32.

Could you please send me the instruction how to debug and fix this issue?

 

Regards,

Anouar 

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pumaju1808
Scholar
Scholar
11,400 Views
Registered: ‎08-14-2007

How are you connecting your custom IP, do you have a state machine where you manage the AXI signals in your IP??, or what do you do with the AXI signals that you receive from the bus??

 

 

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bbinb
Adventurer
Adventurer
10,162 Views
Registered: ‎07-09-2014

Hi,

 

I have the exact same problem. The problem is accessing PL side from PS. I was working on Adam's tutorials and I realized that I can't communicate with PL side: For example driving XADC or creating a peripheral and accessing via AXI-L port.

 

When I debug the code and step into Xil_Out32 function it crashes and the error is:

 

Error while handling inferior event

Remote failure reply : E01

 

Still couldn't find a solution looking for a help. Thanks in advance,

 

bbinb

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masrut
Observer
Observer
3,668 Views
Registered: ‎07-30-2015

I have exactly your same problem. Did you solve it ?

In my situation, I have an AMP with Linux running on CPU0 and bare metal on CPU1.

I think it is a problem of initalization related in some way to ps_init.tcl

I still don't understand, but I am sure it is related to that...

 

 

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dclaymidkiffnasa
Observer
Observer
2,028 Views
Registered: ‎06-18-2019

I am also having the same issue.

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dgisselq
Scholar
Scholar
2,019 Views
Registered: ‎05-21-2015

Can you share your AXI core with us at all?

I found some bugs in Xilinx's AXI demo cores this past year that would cause the bus to hang, and I'd be curious to see of those same bugs were in your core(s).

Dan

dclaymidkiffnasa
Observer
Observer
1,987 Views
Registered: ‎06-18-2019

I am using an AXI demo core (DAC source from RFSOC), so this may very well be it! I'll look into your link. Thanks! I'll update if it is the solution

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dgisselq
Scholar
Scholar
1,977 Views
Registered: ‎05-21-2015

The AXI-lite demo core should be easy to fix.  Rather than fix the AXI demo core, though, I just rewrote it.  While one problem with that core appeared easy to fix, there was another problem or two that wasn't quite so clear to me.

Dan

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dclaymidkiffnasa
Observer
Observer
1,971 Views
Registered: ‎06-18-2019

I'm starting to think that my issue is actually related to my PS DDR4 configuration. For some reason, a Preset doesn't seem to be available in the Zynq IP configuration tool for the Micron MTA4ATF51264HZ-2G6E1 SODIMM that is installed on the ZCU111... Guess I need to figure out how to configure that properly, though I'm having difficulty finding out how. If I'm still having issues with the interface once I figure this out, I'll replace the AXI-lite core. Thanks!

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dclaymidkiffnasa
Observer
Observer
1,956 Views
Registered: ‎06-18-2019

I was correct about my DDR configuration being off. Embarrassingly, all I needed to do was run the "Block Automation Tool" to set up the correct presets.

I didn't realize this because they don't include any examples with the RFSOC on setting up the processor, but it tuurns out that the process is identical to the MPSOC