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Observer
Observer
4,387 Views
Registered: ‎01-04-2013

Wrong MIG DDR3 ui_clk propagation

Hallo *,

 

Did anyone expirienced, that the frequency of the ui_clk comming from the MIG7Series in a BlockDesign is incorrect propagated to the clock output net. It occured when i changed the DDR3 PHY clock frequency from 800 MHz to 600MHz that results in a ui_clk change from 200MHz to ~150MHz, but the propagated clock frequency constraint stayed at 200 MHz.

I discovered it, because the BaudRade calculation of the UartLite was wrong as a result of  that wrong propagation. Finally Uart was working now at 115200/200 * 150 = 86400.

The same error when changing the frequency in the opposite direction.

It seems that the calculation routines are not invoked to recalculate the ui_clk frequency on any change after the first setup?!

 

Greets,

djungewelter

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Xilinx Employee
Xilinx Employee
4,347 Views
Registered: ‎09-20-2012

Hi @djungewelter

 

Which version of vivado are you using?

Are you checking report_clocks output on implemented design to confirm the ui_clk frequency?

Try regenerating the block design output products.

 

 

Thanks,
Deepika.
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Observer
Observer
4,333 Views
Registered: ‎01-04-2013

First, thanks for your fast reply.

 

I tried 2016.2 2016.3 and 2016.4 in an copied and each time upgraded version of the project. All are showing this behaviour.

For sure i regenerated the output products, already several times. Maybe this Vivado needs a total clean folder and project regeneration with tcl scripts?! But this cannot be the right solution!

The timing report does not explicitly show ui_clk, whats definitly strange...

But in the block design design, the output pin property "Frequency (MHz)" of ui_clk on the mig block is 150.060024 MHz, but on the oscilloscope i measure 200 MHz. Thats what i also expect from the mig settings. The "Frequency (MHz)" property cannot be changed manually. As a result the internally propagated 150.060024 MHz leed into at least wrong setup of uart baud rate, but more may be affected.

 

Greets,

djungewelter

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Xilinx Employee
Xilinx Employee
4,324 Views
Registered: ‎09-20-2012

Hi @djungewelter

 

Can you post the report_clocks output here?

 

Are you saying that ui_clk should be 200Mhz? What frequency did you choose for memory clock?

Thanks,
Deepika.
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Observer
Observer
4,318 Views
Registered: ‎01-04-2013

The memory clock is 800MHz.

We are using SO-DIMM MT8KTF51264-HZ-1G6. The Memory is working, calibration completes, all fine.

Memory test are successfull. But Uart gets wrong information for its BaudRate Calculation, since a measure the ui_clk to 200 MHz but the clock net property is 150.060024 MHz. I measred the ui_clk with a Scope after routing it to an ODDR and to an output pin.

Input Clock is 200 MHz, Reference Clock is the same.

 

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Xilinx Employee
Xilinx Employee
4,313 Views
Registered: ‎09-20-2012

Hi @djungewelter

 

The report_clocks output shows correct frequency of 200Mhz. 

 

clk_pll_i                                                                                                                                                  5.000       {0.000 2.500}   P,G         {system_i/mig_7series_0/u_mb_system_mig_7series_0_0_mig/u_ddr3_infrastructure/gen_ui_extra_clocks.mmcm_i/CLKFBOUT}

  

Thanks,
Deepika.
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Observer
Observer
4,309 Views
Registered: ‎01-04-2013

Ok, but the main problem i have is: The Uart Baud Rate calculation in the background is wrong, because the clock net frequency property in the block design is 150.060024 MHz instead of the 200 MHz

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Observer
Observer
4,293 Views
Registered: ‎01-04-2013

I tested to resetup the whole project in a clean folder, using the project tcl and block design tcl scripts (that need to be modified to do this clean project build (--> remove mig_a.prj, mig_b.prj and mb_system.bd from the project build script ).

Now the net property Frequency is back to the correct 200 MHz, BUT still this cannot be the solution and would claim this is a Vivado Bug that need to be fixed!

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Xilinx Employee
Xilinx Employee
4,240 Views
Registered: ‎08-02-2007

hi,

 

would that be possible to share the project? a change request can be filed once the issue is replicable.

 

--hs

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Observer
Observer
4,209 Views
Registered: ‎01-04-2013

I tried to create a minimal project out of an example project to reproduce the behaviour, but it didn't. And also in my project, after recreating it in a total clean way as described before, the behaviour didn't came up again. Even after several times changing the DDR Clk Frequency.

So acutally and unfortunatly there is no faulty project to analyse regarding this issue.

 

Greets,

djungewelter

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Visitor
Visitor
903 Views
Registered: ‎10-09-2018

Hi,

 

I have experienced the same issue as described earlier: the ui_clk clock frequency parameter remains unchanged if the DDR clock is changed. The frequency is ok, just the parameter is wrong. I don't know how could I modify that parameter, it is really annoying.

 

Regards,

Lorant 

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