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Explorer
Explorer
4,567 Views
Registered: ‎02-13-2012

XMD 'connect mb mdm' problems, including resetting the FPGA's programming

I have spent several days (not continuously) searching the Xilinx forums for any discussion of a similar issue and two weeks trying different things.  While there are some discussions are close, none quite describe nor solve the following issue.

Our HW:

  • Custom board (not new), with 17 Virtex7 2000T chips.
  • JTAG interface buffers and independently distributes TCK and TMS to each FPGA.
  • 19.2 MHz master clock (buffered and distributed independently to each FPGA)
  • Windows 7 host PC
  • Digilent cable (tried at a variety of TCK speeds, and with different Xilinx supplied plug-ins)


Xilinx Tools and IP:

  • Vivado 2013.4
  • XDM and LabTools (ISE) 14.7
  • Microblaze and MDM ported from earlier EDK design to the Vivado IP Integrator, and fine tuned by our FAE.
  • Internal sys_reset only (MB/MDM block's reset input is tied to '0' during instantiation)
  • No external memory (MB uses BRAM).


All 17 FPGAs have a single MB + MDM + IOModule + SysReset + SysClock instance.  All are based on a common design and only the top level IO signal connections change.  (See attached PDF and BD files, which were generated by Vivado.)  All non-core RTL instance blocks are routed through the IOModule's memory mapped interface "bus".

 

Completely external to the MB/MDM/IOM core, there is a simple binary counter which divides the incoming 19.2MHz master clock and causes 17 LEDs (1 per FPGA) on the board to blink at ~0.6 Hz.  The master clock is received and immediately passed through a BUFG before being sent to the counter and the MB (and a few other places).

The normal sequence for testing the board using the FPGAs is as follows.

I open a separate XMD shell and successfully can download all 17 FPGAs.  The XMD command line is:


fpga -f (path and name of .bit file) -cable type xilinx_tcf -debugdevice devicenr [N]

 

Note, the "digilent_plugin" cable type was used.  It was changed to xilinx_tcf as recommended by this AR: http://www.xilinx.com/support/answers/57129.html


A typical download log from the XMD console is:


Programming Bitstream -- (path and name of .bit file)
Fpga Programming Progress ............10.........20..Done
Successfully downloaded bit file.

JTAG chain configuration
--------------------------------------------------
Device   ID Code        IR Length    Part Name
 1       236b3093          24        XC7V2000T
 2       236b3093          24        XC7V2000T
 3       236b3093          24        XC7V2000T
 4       236b3093          24        XC7V2000T
 5       236b3093          24        XC7V2000T
 6       236b3093          24        XC7V2000T
 7       236b3093          24        XC7V2000T
 8       236b3093          24        XC7V2000T
 9       236b3093          24        XC7V2000T
10       236b3093          24        XC7V2000T
11       236b3093          24        XC7V2000T
12       236b3093          24        XC7V2000T
13       236b3093          24        XC7V2000T
14       236b3093          24        XC7V2000T
15       236b3093          24        XC7V2000T
16       236b3093          24        XC7V2000T
17       236b3093          24        XC7V2000T

0

 


After the downloads, all 17 LEDs are blinking at this point.

Then I send a "connect mb mdm -cable type xilinx_tcf -debugdevice devicenr [N]" to each FPGA.  At this point, XMD will intermittently connect to the FPGA correctly, or fail in one of several ways.  XMD session message logs for each kind of result:

  • XMD successfully connects

 

JTAG chain configuration
--------------------------------------------------
Device   ID Code        IR Length    Part Name
 1       236b3093          24        XC7V2000T
 2       236b3093          24        XC7V2000T
 3       236b3093          24        XC7V2000T
 4       236b3093          24        XC7V2000T
 5       236b3093          24        XC7V2000T
 6       236b3093          24        XC7V2000T
 7       236b3093          24        XC7V2000T
 8       236b3093          24        XC7V2000T
 9       236b3093          24        XC7V2000T
10       236b3093          24        XC7V2000T
11       236b3093          24        XC7V2000T
12       236b3093          24        XC7V2000T
13       236b3093          24        XC7V2000T
14       236b3093          24        XC7V2000T
15       236b3093          24        XC7V2000T
16       236b3093          24        XC7V2000T
17       236b3093          24        XC7V2000T

MicroBlaze Processor Configuration :
-------------------------------------
Version............................8.50c
Optimization.......................Performance
Interconnect.......................AXI-LE
MMU Type...........................No_MMU
No of PC Breakpoints...............1
No of Read Addr/Data Watchpoints...0
No of Write Addr/Data Watchpoints..0
Instruction Cache Support..........off
Data Cache Support.................off
Exceptions  Support................off
FPU  Support.......................off
Hard Divider Support...............off
Hard Multiplier Support............on - (Mul32)
Barrel Shifter Support.............on
MSR clr/set Instruction Support....on
Compare Instruction Support........on
Data Cache Write-back Support......off
Fault Tolerance Support............off
Stack Protection Support...........off

Connected to "mb" target. id = 0
Starting GDB server for "mb" target (id = 0) at TCP port no 1234

 

 

  • an FPGA will become un-programmed.  (LED stops blinking.  DONE signal goes low -- verified by Impact.)  


JTAG chain configuration
--------------------------------------------------
Device   ID Code        IR Length    Part Name
 1       236b3093          24        XC7V2000T
 2       236b3093          24        XC7V2000T
 3       236b3093          24        XC7V2000T
 4       236b3093          24        XC7V2000T
 5       236b3093          24        XC7V2000T
 6       236b3093          24        XC7V2000T
 7       236b3093          24        XC7V2000T
 8       236b3093          24        XC7V2000T
 9       236b3093          24        XC7V2000T
10       236b3093          24        XC7V2000T
11       236b3093          24        XC7V2000T
12       236b3093          24        XC7V2000T
13       236b3093          24        XC7V2000T
14       236b3093          24        XC7V2000T
15       236b3093          24        XC7V2000T
16       236b3093          24        XC7V2000T
17       236b3093          24        XC7V2000T
ERROR: Could not detect MDM peripheral on hardware. Please check:
        1. If FPGA is configured correctly
        2. MDM Core is instantiated in the design
        3. If the correct FPGA is referred, in case of multiple FPGAs
        4. If the correct MDM is referred, in case of a multiple MDM system

 

 

XMD will report that the JTAG device (the Digilent cable) identifier is invalid

 


JTAG chain configuration
--------------------------------------------------
Device   ID Code        IR Length    Part Name
 1       236b3093          24        XC7V2000T
 2       236b3093          24        XC7V2000T
 3       236b3093          24        XC7V2000T
 4       236b3093          24        XC7V2000T
 5       236b3093          24        XC7V2000T
 6       236b3093          24        XC7V2000T
 7       236b3093          24        XC7V2000T
 8       236b3093          24        XC7V2000T
 9       236b3093          24        XC7V2000T
10       236b3093          24        XC7V2000T
11       236b3093          24        XC7V2000T
12       236b3093          24        XC7V2000T
13       236b3093          24        XC7V2000T
14       236b3093          24        XC7V2000T
15       236b3093          24        XC7V2000T
16       236b3093          24        XC7V2000T
17       236b3093          24        XC7V2000T
ERROR:
    Invalid JTAG device list Digilent/210205331952A=jsn-JtagHs1-210205331952A

 

 

XMD reports that it cannot obtain the JTAG list (even though it just did download the FPGAs and report the list)

 


JTAG chain configuration
--------------------------------------------------
Device   ID Code        IR Length    Part Name
 1       236b3093          24        XC7V2000T
 2       236b3093          24        XC7V2000T
 3       236b3093          24        XC7V2000T
 4       236b3093          24        XC7V2000T
 5       236b3093          24        XC7V2000T
 6       236b3093          24        XC7V2000T
 7       236b3093          24        XC7V2000T
 8       236b3093          24        XC7V2000T
 9       236b3093          24        XC7V2000T
10       236b3093          24        XC7V2000T
11       236b3093          24        XC7V2000T
12       236b3093          24        XC7V2000T
13       236b3093          24        XC7V2000T
14       236b3093          24        XC7V2000T
15       236b3093          24        XC7V2000T
16       236b3093          24        XC7V2000T
17       236b3093          24        XC7V2000T
ERROR:
    Failed to obtain JTAG device list

 

 

As mentioned, this board is not a new design.  We have successfully been using and testing it for 6 months.  What is new is the update to the Xilinx tools (from Vivado 2013.2 to 2013.4, from XMD 14.6 to 14.7, from EDK/SDK 13.2 thru 14.4 to 14.7), the Xilinx IP (from MB 9.0 to 9.2, MDM 3.0 didn't change), and a switch from using Chipscope ICON/VIO for the HW IO test RTL to MB/MDM/IOM memory map based testing of the HW IO RTL.

 

Finally, I have observed that the connect problems seem to have some correlation to the number of FPGAs in the design.  I have another board with only two V7 2000T chips and it almost never fails.  And another board with fifteen V7 2000T chips and it fails at about the same rate as the 17 chip board.

 

If there are any debugging suggestions, I am eager to try them.  Of course, the ideal is rock-solid solution.  :-)

 

Regards,
Mark

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2 Replies
Highlighted
Observer
Observer
3,195 Views
Registered: ‎08-23-2015

Hello, 

how you resolved this issue..?  i facing issue. after downloading elf the programmed bit file getting erased and done pin going low. 

 

does it issue with mdm, elf detecting as bit file ???

 

i am working with vivado 2015.1, the bit file with mdm working fine earlier, sunddenly it stop taking elf and getting erase FPGA it self after download elf.

 

i did reset_project and ran the implementation and generated bit file.. the issue existed for all subsequent builds.

 

 

Thanks.

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Highlighted
Explorer
Explorer
3,170 Views
Registered: ‎02-13-2012

Yes, it was solved.  It was a bug in XMD -- an unititialzed buffer was used to create and eventually transmit the connect command to the target FPGA.  Certain bits of the buffer, if in the wrong state, caused the misbehavior.  The behavior was intermittent and random because the uninitialized buffer's contents depended on whatever the prior process happened to leave in that memory location.

 

It took a team of 3 Xilinx XMD developers to visit on-site and verify for themselves that the hardware, the cable, and the PC's configuration weren't the cause.  Then that was followed by gathering logs using different logging settings for several weeks by me and sending every incident of trouble to them, until the Xilinx engineer spotted the incorrect buffer bits that caused an FPGA to become unprogrammed.  After that, he quickly found the unitialized buffer.

 

The temporary solution was to use a patch Xilinx supplied.  The next release of XMD contained the correction and the patch was not needed after that.

 

Since you are using a much later version of the Xilinx tools, I doubt that the cause of the problem I had back then and the cause of the problem you have now are the same.  I suggest you file a Tech Support ticket.

 

Good luck

 

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