10-27-2019 01:35 PM
I am trying to implement a microblaze MCS IP on Basys3 board using Vivado 2018.3.
I am able to generate ip, instantiate the ip and synthesize the design in Vivado.
Problem occurs in Xilinx SDK when creating the new project... "Hardware Platform Specification".
I select the target hardware specification as "<project name>.src/ip/sources_1/ip/microblaze_mcs_0/microblaze_mcs_0.xml" then there is a little bit of processor churn before the console spits out the error:
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14:30:55 ERROR : (XSDB Server)ERROR: [Hsi 55-1518] No design name specified
14:30:55 ERROR : Failed to closehw "/home/*******/src/xilinx_lab/*******/mcs_0/mcs_0.srcs/sources_1/ip/microblaze_mcs_0/microblaze_mcs_0.xml"
Reason: ERROR: [Common 17-39] 'hsi::close_hw_design' failed due to earlier errors.
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I'm guessing this is a trivial error associated with me not really knowing how to setup the SDK workspace. But I don't know where to start sorting this out.
Any suggestions? Thanks!
10-27-2019 06:41 PM
10-27-2019 06:41 PM