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simchask
Explorer
Explorer
6,214 Views
Registered: ‎11-23-2017

(XSDB Server)ERROR: [Hsi 55-1545] Problem running tcl command

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After exporting the hardware and bit file for the SDK, I luanch the SDK.

However, when I try to create the example 'hello world' project, it fails.

 

The SDK log contains:

13:06:20 INFO  : Registering command handlers for SDK TCF services
13:06:20 INFO  : Launching XSCT server: xsct.bat -interactive C:\Users\Owner\Documents\adi\hdl\projects\ad9739a_fmc\ac701\ad9739a_fmc_ac701.sdk\temp_xsdb_launch_script.tcl
13:06:21 INFO  : XSCT server has started successfully.
13:06:21 INFO  : Successfully done setting XSCT server connection channel  
13:06:21 INFO  : Processing command line option -hwspec C:/Users/Owner/Documents/adi/hdl/projects/ad9739a_fmc/ac701/ad9739a_fmc_ac701.sdk/system_top.hdf.
13:06:21 INFO  : Successfully done setting SDK workspace  
13:07:00 ERROR : (XSDB Server)ERROR: [Hsi 55-1545] Problem running tcl command ::sw_intc_v3_7:
13:07:00 ERROR : (XSDB Server):generate : can't read "source_name(13)": no such element in array
    while executing
"string compare -nocase $source_name($i) "system""
    ("foreach" body line 18)
    invoked from within
"foreach periph $periphs {
        #update global array of Interrupt sources for this periph
        intc_update_source_array $periph

        lappend ..."
    (procedure "xredefine_intc" line 21)
    invoked from within
"xredefine_intc $drv_handle $file_handle"
    (procedure "xdefine_canonical_xpars" line 72)
    invoked from within
"xdefine_canonical_xpars $drv_handle "xparameters.h" "Intc" "DEVICE_ID" "C_BASEADDR" "C_HIGHADDR" "C
13:07:00 ERROR : (XSDB Server)_KIND_OF_INTR" "C_HAS_FAST" "C_IVAR_RESET_VALUE" "C..."
    (procedure "::sw_intc_v3_7::generate" line 57)
    invoked from within
"::sw_intc_v3_7::generate axi_intc"
ERROR: [Hsi 55-1442] Error(s) while running TCL procedure generate()
1 Solution

Accepted Solutions
ibaie
Xilinx Employee
Xilinx Employee
7,258 Views
Registered: ‎10-06-2016
Hi @simchask,

It seems that the BSP generation had an issue when running the interrupt controller generation part.

What device are you using? and which OS BSP (standalone or FreeRTOS)?

Regards

Ibai
Don’t forget to reply, kudo, and accept as solution.

View solution in original post

10 Replies
ibaie
Xilinx Employee
Xilinx Employee
7,259 Views
Registered: ‎10-06-2016
Hi @simchask,

It seems that the BSP generation had an issue when running the interrupt controller generation part.

What device are you using? and which OS BSP (standalone or FreeRTOS)?

Regards

Ibai
Don’t forget to reply, kudo, and accept as solution.

View solution in original post

simchask
Explorer
Explorer
6,152 Views
Registered: ‎11-23-2017

These problems arose from changes I made to the block design. I removed signals that were concatanated into a wide signal of interrupts. Strangely, the whole thing validated and was made into a bitstream without warning.

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tim_severance
Scholar
Scholar
5,997 Views
Registered: ‎03-03-2017

@simchask, What was the fix?   I am having the same exact problem with my design, failing also on the sw_intc_v3_7 block.

Thanks.

Tim

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jmackin
Newbie
Newbie
5,947 Views
Registered: ‎04-10-2018

This is marked solved yet shows no solution. I am having the exact same problem with the interrupt controller.

Thanks,

Jeff

tim_severance
Scholar
Scholar
5,943 Views
Registered: ‎03-03-2017

@jmackin,

   In my block design my concat block going into the interrupt controller had an input that was floating.   I believe once I reimplemented without a floating input then things started working.  

Tim

jmackin
Newbie
Newbie
5,931 Views
Registered: ‎04-10-2018

@tim_severance

That worked! Thanks!

-Jeff

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tim_severance
Scholar
Scholar
5,927 Views
Registered: ‎03-03-2017

@jmackin,

   Great news!

Tim

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simchask
Explorer
Explorer
5,799 Views
Registered: ‎11-23-2017

I had to rewrite the interface of the modules being instantiated to account for the fact that I deleted some pins.

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othane
Newbie
Newbie
3,749 Views
Registered: ‎12-31-2018

Thank you !! ... you would think this could be a validation error ?!?!?!

gitesh@xilinx
Visitor
Visitor
415 Views
Registered: ‎06-13-2019

I did the same thing... I have connected the input of my concat ip to the interrupt o/p of the uartlite... and there is no floating input in my concat ip.... things are still not working...

bu one floating i/p (aux_reset_in) and one floating o/p (peripheral_reset) are still there in Processor System Reset ip ... Can you please tell me whether these two floating pins are creating the problem or not ...

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