cancel
Showing results for 
Show  only  | Search instead for 
Did you mean: 
Highlighted
Adventurer
Adventurer
932 Views
Registered: ‎11-04-2010

XSpi_Transfer() hangs on unknown opcodes

I’ve been migrating a design from one flash device to another and have come across a problem. According to PG153, when configured in Quad mode the AXI Quad SPI peripheral parses the opcodes it transmits. If it doesn’t like one, the “command error” flag gets set, but the peripheral finishes the transaction in standard SPI mode:

spi_command_error.PNG

I ran across such an instruction: 0xC4, or DIE ERASE for the MT25Q flash from Micron. But the transaction was not finished, and as a result the corresponding call to XSPI_Transfer() hung in this loop:

/*
 * Wait for the transfer to be done by polling the
 * Transmit empty status bit
 */
do {
	StatusReg = XSpi_IntrGetStatus(InstancePtr);
} while ((StatusReg & XSP_INTR_TX_EMPTY_MASK) == 0);
0 Kudos
6 Replies
Highlighted
524 Views
Registered: ‎03-22-2013

Hello Xilinx,

Do you have any feedback about this issue ?

I'm facing the same issue with vivado 2018.2 and axi Quad SPI 3.2.

@vertreko If you have a solution could you please tell me? Thanks in advance

 

Best reagards

 

0 Kudos
Highlighted
Adventurer
Adventurer
483 Views
Registered: ‎09-11-2018

I encountered something similar:
https://forums.xilinx.com/t5/Processor-System-Design/XST-SPI-COMMAND-ERROR-when-sending-command-to-QSPI-flash/td-p/1044216

I managed to get this even for a command that should be "supported", don't know yet why.

0 Kudos
Highlighted
Scholar
Scholar
462 Views
Registered: ‎04-13-2015

From what I know about thje Quad SPI module is there are no user control over the number of lanes used for the op-code, address, and data,  For example, all commands with parameters are using 1 lane, so a flash chip set to operate in dual or quad will not "talk the same language".  When a supported opcode is used for op-code / adress / data then make sure the flash is set to operate according in the "basic" mode, which typically involves 1-1-1, 1-2-2 or 1-4-4 exchanges.

0 Kudos
Highlighted
Visitor
Visitor
444 Views
Registered: ‎05-17-2018

Hi,

I'm working with @christian.lambricht on this. The documentation of the core (PG153 v3.2) is ambiguous about the behavior of the core about the command error.  From the description of Command Error in Table 2-13, it is said that the core completes the SPI transactions. 

Table 2-13.png

On page 55 of the documentation it is being said that when the core does not recognise the command being sent to the flash it will not execute the command an raise the Command Error interrupt.

page 55.png

In our particular case it seems that the core is not executing the command because when we send the C4 command with 3 dummy bytes the command error is raised and the status of the is ready (bit 0 of flash status register).

Anyway what I don't understand is why the core does not recognize the die erase command (C4) since it is supported by the flash ?

As a work arround we are using the sector erase command (D8) which work as expected.

Regards,

0 Kudos
Highlighted
Observer
Observer
385 Views
Registered: ‎12-29-2012

Hello to all.

I have a like problem with MT25q256 flash.

Under data sheet youcan see C4 DIE ERASE command is supported only by XIP mode(p.67)

Try to use core with XIP option.

BR.

0 Kudos
Highlighted
Participant
Participant
185 Views
Registered: ‎05-17-2018

Sorry for replying to this old thread, but I have this same exact issue... weird thing is that everything worked perfectly for a while and the stopped when the next day I tried to rebuild the same vivado project.

I'm using vivado 2019.2 and a spansion qspi flash (S25FL256S).

0 Kudos