XUPV5-LX110T Problems with the EDK 11.3 ( DDR2 memory and FSL)

[rittersport3]

Hi folks!

So, like a normal newbie, I've been having some trouble implementing some pretty standard  stuff. My last objective is having a microblaze that reads images from the CF card  display them, and them sends the pixel's positions to an external peripheral that should perform some transform on them.
So far I took that Xilinx Slideshow example and tried to develop it.

But.

First , DDR2 . Like in this thread :  here

I've  not been able to create with bsb a functioning system with mpmc module.
I would follow the steps of creating a 505 board, and in the end I will change the in Project->Options the processor for the 110T.  After that the Iodelay errors pop up. I 've tried to generate a new mpmc as well as editing te ucf to counter this problem.

Does anybody knows how to get around ?

Second.FSL, standard peripheral.

I've been trying to run the simple peripheral wizard thing, creating a FSL connection from processor to peripheral and running the test code on SDK. I can export to SDK, but there, i cannot get any result from the Peripheral other than 0 what, since I am using the standard adder wizard-built construct, doesn't seems right.

Well, I am attaching my files now, and If anyone could look at them and give suggestions, it would be really kind and helpful.

Thanks a lot!

Ps : Since I need DDR2 memory, I used the base example and just added a FSL link between my peripheral and the microblaze. The software is in the SDK\SDK_Workspace folder.

I cannot attach the file so I hosted it on rapidshare.

http://rapidshare.com/files/318882136/Project.zip.html

[grando]

Hi,

I also work with this board, EDK 11.2, and had the same problem with the DDR2.

It seems that the memory controller supplied so far by Xilinx in the board support package does not work out of the box with EDK 11.x. So you will need to edit the generated UCF file to get the memory controller running. Removing all the RLOC_ORIGN constraints from it solved the problem for me.

Additionaly, it may be interesting to update the memory part number (for me, it's a Micron MT4HTF3264HY-667F1).

Source: MPMC data sheet, "Migrating an MPMCv4 Virtex-5 DDR2 Design to MPMCv5".

I managed once to make two MicroBlaze communicate with each other using FSL, but never tried with a periheral. I'm afraid I can't help you further with this part.... (Couldn't manage to download your project)

Carmela

[rittersport3]

Hey Carmela,

Thanks a lot!

I will try to fix the memory thing and I'll tell you the results.

I am very grateful.

Pedro

[rittersport3]

Uh well,

I tried to "fix" the ucf file, but I haven't got any further succes, so I am posting here the ucf file and, if anyone could tell me what is missing, I would very grateful!

Thanks a lot!

 
Pedro

[grando · Accepted solution]

Hi,

your .ucf looks like the one for ML505 (regarding SDRAM), which is a little bit different from mine. I'm not an expert, so I can't say if this is what is causing you problems.

Just to be sure, are you using the correct EDK BSB support pack for XUPV5?

You get them here: http://www.xilinx.com/univ/xupv5-lx110t-bsb.htm

Furthermore, in the MPMC data sheet they also mention removing some parameters from the MHS file. (in my case, however, these parameters were not present)

Best luck,

Carmela

[rittersport3]

Hi,

Yes, that was it!

I was not using the BSB support pack.

So, used the BSB support pack , and , like you suggested, deleted the constraints on the end File.

It Worked!

Thanks a lot Carmela!

Pedro