Xilinx CORE Generator produced "IP " to use in edk 10.1

[likeyou614]

I use xilinx CORE Generator to produce one " rom "
Then add to edk, produce the following error information
Where it is problematic, ask everybody
Thanks ......

ERROR:NgdBuild:604 - logical block
   'button_led_0/button_led_0/USER_LOGIC_I/ml507_1/rom1' with type
   'rom64k_24bit' could not be resolved. A pin name misspelling can cause this,
   a missing edif or ngc file, or the misspelling of a type name. Symbol
   'rom64k_24bit' is not supported in target 'virtex5'.

Partition Implementation Status
-------------------------------

  No Partitions were found in this design.

-------------------------------

NGDBUILD Design Results Summary:
  Number of errors:     1
  Number of warnings:   1

One or more errors were found during NGDBUILD.  No NGD file will be written.

Writing NGDBUILD log file "dipsw_led2.bld"...
ERROR:Xflow - Program ngdbuild returned error code 2. Aborting flow execution...

[golson]

  Here is what I think may be your problem.  Under pcores and under your core directory

for example:

directory below: 

pcores\rx_v1_01_a

Has four subdirectories.

data  hdl netlist and devl 

check your netlist directory for the ngc file that is your rom.

you should have for example  under HDL  rom.v or rom.vhdl  and under the netlist directory you should have rom.ngc.

[jke2553]

Yes, I agree that that's likely your problem. Also, perform the following steps in your data directory:

• MPD file - Add 'OPTION STYLE = MIX' with other options
• PAO file - Append all of the VHDL source files in the form 'lib <peripheral name> <VHDL file name sans extention> VHDL'
• BBD file - Create this file with the same name as the MPD or PAO file, but with a .bbd extension. Populate with:

  • FILES 
    <name of ngc> (ie plb_fifo.ngc) 

 I do have a related question though - how do you avoid synthesizing twice (once to create the ngc for the netlist directory and once when you synthesize your whole design)? Is it prudent to change the IMP_NETLIST to false?

thanks, and hopefully that's helpful,

Jeremy

[likeyou614]

Thanks 
I have solved the problem!

[mariuszgrad]

Hi,

*.bbd is used afterwards to copy all *.ngc files listed there to implementation/ directory and *.pao to extend synthesis/*_xst.prj file.

Therefor if you have a component (hard macro - like busmacros for eapr) which is not generated by coregen then either you can create pcore from him or edit synthesis/* files directly.

---

 I do have a related question though - how do you avoid synthesizing twice (once to create the ngc for the netlist directory and once when you synthesize your whole design)? Is it prudent to change the IMP_NETLIST to false?

---

I think you have to synthesize twice.

1. xst each components individually

- under system.vhd all attached components are black_boxed, this means that system.ngc does not contain all component

2. ngdbuild which compiles everything together and creates one *.ngd file (that file includes *.ngc's + *.ucf file).

You can have a look on chapters 2-4  of dev.pdf about different design flows.

Also have a look on guided map & par (p184, p203), i think that these are responsible for "SmartGuided" option under ISE.

Greetings, Mariusz.

Message Edited by mariuszgrad on 03-13-2009 03:33 AM

[vgs]

Hai,

I'm in great need of displaying an image on VGA port through spartan 3e starter kit using EDK9.2i as a part of my pg project.

My aim is to convert the image into its corresponding RGB values,store it in a .coe file. create a xilinx ip core of ROM module into which this file is downloaded.

But I don't how to connect this module to EDK.Kindly help me with the steps in performing this process.

Kindly help me.

Thanks in Advance

Thanks and Regards

vgs