Xilinx FSBL getting printed

[gayathri90]

Hi all,

  I have been trying an example for implementing FIR filter.

  The problem is whenever i am trying to print out my results,

   the Xilinx FSBL is getting printed.

  What could be the cause of this?

 Can anybody help me over this issue?

Thanks,

Gayathri

[smarell]

"FSBL_DEBUG" flag would have been set in your project. If you don't want to see FSBL log then you should remove this flag.

For more information on this flag, refer to "Setting FSBL Compilation Flags" section of http://www.xilinx.com/support/documentation/user_guides/ug821-zynq-7000-swdev.pdf

[gayathri90]

Why is that appearing only for this particular project?

Also, the program stops executing after printing the FSBL.

And a pop window appears asking me to power cycle the board for the next use.

I am using Vivado 2014.1 and zedboard

[smarell]

Can you please post the fsbl log here?

[gayathri90]

Xilinx First Stage Boot Loader
Release 14.7/2013.3 Apr 7 2014-14:41:50
Devcfg driver initialized
Silicon Version 1.0
Boot mode is SD
SD: rc= 0
SD Init Done
Flash Base Address: 0xE0100000
Reboot status register: 0x60000000
Image Start Address: 0x00000000
Partition Header Offset:0x00000C80
Partition Count: 3
Partition Number: 1
Header Dump
Image Word Len: 0x000F6EC0
Data Word Len: 0x000F6EBF
Partition Word Len:0x000F6EC0
Load Addr: 0x00000000
Exec Addr: 0x00000000
Partition Start: 0x000065D0
Partition Attr: 0x00000020
Partition Checksum Offset: 0x00000000
Section Count: 0x00000001
Checksum: 0xFFD14B7F
Bitstream
Encrypted
In FsblHookBeforeBitstreamDload function
PCAP:StatusReg = 0x40000F30
PCAP:device ready
PCAP:Clear done
Level Shifter Value = 0xA
Devcfg Status register = 0x40000A30
PCAP:Fabric is Initialized done
PCAP register dump:
PCAP CTRL 0xF8007000: 0x4200E07F
PCAP LOCK 0xF8007004: 0x00000002
PCAP CONFIG 0xF8007008: 0x00000508
PCAP ISR 0xF800700C: 0x5802000F
PCAP IMR 0xF8007010: 0xFFFFFFFF
PCAP STATUS 0xF8007014: 0x00077A30
PCAP DMA SRC ADDR 0xF8007018: 0x00100001
PCAP DMA DEST ADDR 0xF800701C: 0xFFFFFFFF
PCAP DMA SRC LEN 0xF8007020: 0x000F6EC0
PCAP DMA DEST LEN 0xF8007024: 0x000F6EBF
PCAP ROM SHADOW CTRL 0xF8007028: 0xFFFFFFFF
PCAP MBOOT 0xF800702C: 0x00000000
PCAP SW ID 0xF8007030: 0x00000000
PCAP UNLOCK 0xF8007034: 0x757BDF0D
PCAP MCTRL 0xF8007080: 0x00000000

DMA Done !

FPGA Done !
In FsblHookAfterBitstreamDload function
Partition Number: 2
Header Dump
Image Word Len: 0x00002003
Data Word Len: 0x00002003
Partition Word Len:0x00002003
Load Addr: 0x00100000
Exec Addr: 0x00100000
Partition Start: 0x000FD490
Partition Attr: 0x00000010
Partition Checksum Offset: 0x00000000
Section Count: 0x00000001
Checksum: 0xFFCFC8F5
Application
Handoff Address: 0x00100000
In FsblHookBeforeHandoff function
SUCCESSFUL_HANDOFF
FSBL Status = 0x1
Hello World

[gayathri90]

I am trying for an fir filter (block design done in vivado).

When i printed the results of the fir filter, instead of the results, this is printed

Also, none of the flags were set in my project (as mentioned in the second post)

[smarell]

From the FSBL log, it looks like you have FSBL.elf, .bit file and hello_world.elf files in your bootimage.

Have you included the application of FIR filter to show the results in the boot image?

[gayathri90]

I am really sorry that i don't understand your question.

I had created an empty application in sdk and then imported my code to it. Bit file is generated and exported from vivado

[gayathri90 · Accepted solution]

i think i have figured out the problem...

It was with the linker script.

I generated a new linker script with the code and data sections moved from ddr memory to ram section.

It worked.. :)