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lablondejames
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Registered: ‎06-25-2019

Xilinx SDK FSBL QSPI driver in 2017.4 & 2019.1 with ISSI IS25LP512M

I am reading 0xF8F8F8F8 from our dual parallel configuration of 2x IS25LP512M connected to Xilinx 7020. My environment is using the Xilinx SDK FSBL application project out of the box. The QSPI is viewable @ 0xFC000000 until InitQspi() call is made via the Memory Monitor, then it changes to 0x????????. 

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ritakur
Xilinx Employee
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Registered: ‎09-01-2014

Zynq-7000 QSPI controller only supports 16 MB addressing per device (32 MB for two devices) in Linear mode. Densities greater than 16MB are supported in I/O mode.
In linear mode, the flash memory subsystem behaves like a typical read-only memory with the address starting from 0xFC00_0000
Since you use two 64MB QSPI, FSBL will switch it to IO mode which you cannot see the QSPI address from the memory map directly.
lablondejames
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In our previous design we used the Micron version of the part, n25q_512mb, and had no issues reading like a normal device. Is there something special about the ISSI part? I don't see any special handling in the FSBL between the two.

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lablondejames
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Here is the current FSBL debug info:

 


Xilinx First Stage Boot Loader
Release 2019.1  Jul  2 2019-09:51:20
Devcfg driver initialized
Silicon Version 3.1
Boot mode is QSPI
Single Flash Information
FlashID=0x9D 0x60 0x1A
512M Bits
QSPI is in Dual Parallel connection
QSPI Init Done
Flash Base Address: 0xFC000000
Reboot status register: 0x60402000
Multiboot Register: 0x0000C000
Image Start Address: 0x00000000
Partition Header Offset:0xE8E8F8F8
Bank Selection 116
BankSel 116 != Register Read 0
Bank Selection Failed
Move Image failed
Header Information Load Failed
Partition Header Load Failed
FSBL Status = 0xA00E

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ritakur
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Registered: ‎09-01-2014

Does QSPI standalone example work?
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lablondejames
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I also slowed down the QSPI Controller from 25Mhz (200Mhz/8) to 781.25Khz(200Mhz/256) with no success. I am now using the Xilinx SDK Version 2019.1 Zynq FSBL application project and get the following debug output (see notes below):

 

Xilinx First Stage Boot Loader

Release 2019.1 Jul  3 2019-17:22:21

Devcfg driver initialized

Silicon Version 3.1

Boot mode is QSPI

Single Flash Information

FlashID=0x9D 0x60 0x1A

ISSI 512M Bits

Status Reg=0x40

QSPI is in Dual Parallel connection

Single Flash Information

Flash SR=0x40

QSPI Init Done

Flash Base Address: 0xFC000000

Reboot status register: 0x60402000

Multiboot Register: 0x0000C000

Image Start Address: 0x00000000

Partition Header Offset:0xFDFDFDFD

Bank Selection 126

BankSel 126 != Register Read 0

Bank Selection Failed

Move Image failed

Header Information Load Failed

Partition Header Load Failed

FSBL Status = 0xA00E

 

  • Note small bug in ISSI ID highlighted in red where FlashReadID() function looks at index 0 instead of 1 in FSBL.

I was looking at the status register of the ISSI part to see if the Quad Enable bit was set to 1 (QE = 1).  This didn’t seem to be set at first but also didn’t appear to help functionality when set.

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ritakur
Xilinx Employee
Xilinx Employee
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Registered: ‎09-01-2014

Please don’t stick in FSBL. Maybe there has SI issues on your board. please try other SW like QSPI standalone example or u-boot to see it works or not.

IS25LP512M is a Xilinx supported device in 2019.1. it should work
https://www.xilinx.com/support/answers/50991.html
There are 1.8v and 3.3v devices, which one do you use? Do you set MIO bank with the same voltage?
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