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291 Views
Registered: ‎01-27-2020

Xilinx VC707 FPGA

Hello Team,

I am using Xilinx VC707 FPGA board to mimic my IC architecture. I use BRAM to model 1MB flash. However, when i use data2mem.exe to generate .bit file (to merge firmware and RTL bit file) i see the error attached fig1.png.

 

ERROR:Data2MEM:21 - Bit lane OVERLAP in ADDRESS_SPACE 'pike_river_addr_map.flash'.
'i_estonet40_pmic_dig_top/i_dig_core/i_flash/ram/main_mem_reg_1_0 [0:0]'
'i_estonet40_pmic_dig_top/i_dig_core/i_flash/ram/main_mem_reg_0_0 [0:0]'

.

.

so on till 

'i_estonet40_pmic_dig_top/i_dig_core/i_flash/ram/main_mem_reg_1_63 [63:63]'
'i_estonet40_pmic_dig_top/i_dig_core/i_flash/ram/main_mem_reg_0_63[63:63]'

(screenshot attached)

 

please suggest me on resolving this error.

 

Thanks,

Sanju

 

fig1.PNG
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Moderator
177 Views
Registered: ‎09-12-2007

Re: Xilinx VC707 FPGA

As the error message states; you have a bitlane mismatch. can you share the bmm file?

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143 Views
Registered: ‎01-27-2020

Re: Xilinx VC707 FPGA

Hello,

Please find the attached bmm file. This was when i was trying to use BRAM size 1MB. There were 4 instances of main_mem_reg created and the error was only for main_mem_reg_0 and main_mem_reg_1 for all 32bits(bit lane overlap error).

However when i change the size to 128Kb , I am able to merge the mem file, bmm and bit file and there is only one insatnce of main_mem_reg_0 in the bmm file. However, the *.mem file contents are not placed at the expected adress 0 specified in the bmm file. What can be the issue here? I use data2mem utility to merge *.mem, *.bit and *.bmm files.

Each time i run synthesis and place & route, in the bmm file the PLACED location changes. Can this be an issue as I don't see the data i expect to see at address 0 of BRAM(emulated as flash in the design).

 

Thanks

Sanju 

 

 

 

 

 

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