01-31-2020 03:25 PM
I am using Xilinx VC707 FPGA board to mimic my IC architecture. I use BRAM to model 1MB flash. However, when i use data2mem.exe to generate .bit file (to merge firmware and RTL bit file) i see the error attached fig1.png.
ERROR:Data2MEM:21 - Bit lane OVERLAP in ADDRESS_SPACE 'pike_river_addr_map.flash'.
so on till
please suggest me on resolving this error.
02-14-2020 05:09 PM - edited 02-19-2020 10:54 AM
Please find the attached bmm file. This was when i was trying to use BRAM size 1MB. There were 4 instances of main_mem_reg created and the error was only for main_mem_reg_0 and main_mem_reg_1 for all 32bits(bit lane overlap error).
However when i change the size to 128Kb , I am able to merge the mem file, bmm and bit file and there is only one insatnce of main_mem_reg_0 in the bmm file. However, the *.mem file contents are not placed at the expected adress 0 specified in the bmm file. What can be the issue here? I use data2mem utility to merge *.mem, *.bit and *.bmm files.
Each time i run synthesis and place & route, in the bmm file the PLACED location changes. Can this be an issue as I don't see the data i expect to see at address 0 of BRAM(emulated as flash in the design).