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adventure789
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Registered: ‎07-06-2020

(ZCU 1O2)AXI DMA 7.1 AT S2MM , DATA IS NOT RECEIVING AND WAITING AT BUSY STATE

Hello all ,im newbie to the fpga .Working on a Vivado(2019.1v) design to receive stream data into AXI-DMA from the axi stream fifo. Another side of fifo is connected to external hls data source module(data sent through hls module tdata= 4bytes of data ,tkeep=0xffff,tlast=1).Working on sdk standalone appln and dma-direct register mode , trying to receive data at s2mm(from Fifo) but rx interrupt,data is not receiving. If i connected S2MM to MM2S(loopback) what ever data sent(>4bytes) ,received back perfectly back i can see in gtkterm but didnt get output in hw_ila. So, please help me what mistakes i did (attach the code below).

//*****************************************************code**********************************************

#define MEM_BASE_ADDR ( 0x1000000)

#define TX_BUFFER_BASE (MEM_BASE_ADDR + 0x00100000)
#define RX_BUFFER_BASE (MEM_BASE_ADDR + 0x00300000)
#define RX_BUFFER_HIGH (MEM_BASE_ADDR + 0x004FFFFF)

int
axi_dma_init()
{
uint8_t Status;
Xil_DCacheEnable();

Status = XAxiDma_intialize(DMA_DEV_ID);
return Status;
}

int XAxiDma_intialize(u16 DeviceId)
{
uint8_t Status;
XAxiDma_Config *CfgPtr;

CfgPtr = XAxiDma_LookupConfig(DeviceId);

Status = XAxiDma_CfgInitialize(&AxiDma, CfgPtr);

Status=SetupIntrSystem(&Intc, &AxiDma, TX_INTR_ID, RX_INTR_ID);

XAxiDma_IntrDisable(&AxiDma, XAXIDMA_IRQ_ALL_MASK,
XAXIDMA_DMA_TO_DEVICE);

XAxiDma_IntrDisable(&AxiDma, XAXIDMA_IRQ_ALL_MASK,
XAXIDMA_DEVICE_TO_DMA);

/* Enable all interrupts */
XAxiDma_IntrEnable(&AxiDma, XAXIDMA_IRQ_ALL_MASK,
XAXIDMA_DMA_TO_DEVICE);


XAxiDma_IntrEnable(&AxiDma, XAXIDMA_IRQ_ALL_MASK,
XAXIDMA_DEVICE_TO_DMA);

/* Initialize flags before start transfer test */

TxDone = 0;
RxDone = 0;
Error = 0;
return Status;
}

 

void
dma_receive_data_32b(int *rcv_data,int size,int count)
{
u32 *RxPacket,i,status;
RxPacket = (u32 *)RX_BUFFER_BASE+count;
Xil_DCacheFlushRange((UINTPTR)RxPacket,size);
Xil_DCacheInvalidateRange((UINTPTR)RxPacket,size);
for(i=0;i<size/4;i++){
xil_printf("Add[%x] = %x \r\n",&RxPacket[i],RxPacket[i]);
}
}

void
dma_transmit_data_32b(int *tx_data,int size)
{
int Status,j,Value,i;
u32 *TxBufferPtr;
u32 *RxPacket;

RxPacket = (u32 *)RX_BUFFER_BASE;

TxBufferPtr = (u32 *)TX_BUFFER_BASE;

memcpy(TxBufferPtr,tx_data,size);

Xil_DCacheFlushRange((UINTPTR)TxBufferPtr,size);
Xil_DCacheFlushRange((UINTPTR)RxPacket,size);

XAxiDma_SimpleTransfer(&AxiDma,(UINTPTR) RxPacket,
size, XAXIDMA_DEVICE_TO_DMA);


Status = XAxiDma_SimpleTransfer(&AxiDma,(UINTPTR)TxBufferPtr,
size, XAXIDMA_DMA_TO_DEVICE);
xil_printf("status = %d ",Status);
while((XAxiDma_Busy(&AxiDma,XAXIDMA_DMA_TO_DEVICE)) | (XAxiDma_Busy(&AxiDma,XAXIDMA_DEVICE_TO_DMA)))
{
//xil_printf("dma is busy at transmit");
}

}

calling these functions:

 axi_dma_init();

int test_array2[5]={0};
dma_receive_data_32b(test_array2,16,0);

Thanks & Regards,
Pavan Kumar
Tags (2)
address_editor_dma.png
gtkterm_dma.png
module_dma.png
block_diagram_dma.png
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