(ZCU 1O2)AXI DMA 7.1 AT S2MM , DATA IS NOT RECEIVING AND WAITING AT BUSY STATE
Hello all ,im newbie to the fpga .Working on a Vivado(2019.1v) design to receive stream data into AXI-DMA from the axi stream fifo. Another side of fifo is connected to external hls data source module(data sent through hls module tdata= 4bytes of data ,tkeep=0xffff,tlast=1).Working on sdk standalone appln and dma-direct register mode , trying to receive data at s2mm(from Fifo) but rx interrupt,data is not receiving. If i connected S2MM to MM2S(loopback) what ever data sent(>4bytes) ,received back perfectly back i can see in gtkterm but didnt get output in hw_ila. So, please help me what mistakes i did (attach the code below).