02-16-2021 11:11 AM - edited 02-16-2021 11:12 AM
Hi, I hope you are well.
I have a synthesizable PL custom processor (not implemented by myself), shown in the picture below. I added a ROM (for boot) and RAM, and a UART16550, mapped with addresses provided on the core files. Afterwards, I generated and exported the hardware with the bitstream and created a Vitis platform using the wrapper.xsa. How can I run C codes to it, and check the outputs in the UART (Hello world for example)?
I think I couldn't create an application project because I am not using any PS from the ZCU102. Also, I could not find documentation or tutorial on how I can run C code on custom processors for Xilinx FPGAs.
Can someone guide or point me to documentation or tutorial of how I can run C codes on a PL custom processor, or use it to blink LEDs?
Thank you in advance.
03-12-2021 03:45 PM
As far as I know, you have created some hardware. So, how you could to program it?
Via Vivado ready bitstream with some ROM memory?
Using JTAG external ports to softcore processor?
Via AXI interface from ZCU PS to softcore processor?
There is no easy way as using ready tools until you have some standard instruction set processor and program .elf to ROM.
03-12-2021 04:36 PM
Thank you very much for your reply.
This custom processor, called Flute, is RISC-V based. I have the .coe and .elf files for a few examples, such as Hello world, generated for a different processor, called Potato, also RISC-V based. I modified the .elf file generator of potato to match the address space of Flute. Therefore, I load the .coe in the ROM, and I also add the .elf in the Vivado project (which is usually ignored when generating the bitstream, I am not sure why). But, still, I can't see anything in the serial terminal (After downloading the .bit file to the FPGA).
However, I haven't thought about connecting this processor to the FPGA softcore processor to be able to use it. Do you think that would be the only approach? Because, in the end, I won't be able to have the softcore as part of the project.
03-13-2021 07:36 AM - edited 03-13-2021 07:37 AM
Why can't you use ZYNQ to program IP cores via AXI4? IMO it is the easiest way.
Second option add some external memory like SD-CARD (NON-Volatile) and read it from RISC-V.
ZYNQ = Hard Procesor -> you have one on zcu. And interconnect wouldn't cost many resources.
Microblaze = Soft Procesor -> I don't think this is good idea.
Third way use JTAG ports to your RISC-V and program it normally via some programmer
03-13-2021 08:52 AM
I want to avoid using the ZYNQ processor to have a final design that can be implemented in different Xilinx FPGAs. Therefore, using the PL resources only would be ideal.
I like the SD Card and JTAG ideas. Is there a JTAG programmer you would recommend?
03-14-2021 07:19 PM