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luhb
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Registered: ‎01-23-2020

ZYNQ Cores stopped/suspended

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Hi dear Xilinx community,

at the moment I am learning to work with the ZYNQ architecture and succeeded in doing some tests and even my own HW design (PL) connected to the PS, exchanging data via DMA. I also succeeded in working with external data for my custom logic on an SD-card. I already love the possibilities that ZYNQ architecture and the whole flow provides. But since monday I'm a little bit stuck.

I used to work with ZC702 evaluation board and now have to switch to a platform with more LUT/FF slices, due to the large design I want to connect to the PS. In my institute, we already owned the Mini-ITX-7Z-ASY-G board (7z045 SoC), so I tried to do the most basic tests (Helloworld.c) with that board.

  • Create Vivado Project with board definition files from Zedboard.org (in a previous attempt I also tried just selecting xc7z045ffg900-2 with the same result)
  • Create block diagram, ticked UART1 for SDK later on, ran block automation, created wrapper, synthesized, implemented and wrote bitstream and hardware file (hdf)
  • In XSDK, I created a new application project, imported the hardware and created a new BSP. From the list of templates I selected Helloworld
  • Programmed the FPGA successfully
  • Run Helloworld with System Debugger

This is what xsdb shows:

Info: ARM Cortex-A9 MPCore #0 (target 2) Stopped at 0xffffff28 (Suspended)
Info: ARM Cortex-A9 MPCore #1 (target 3) Stopped at 0xffffff34 (Suspended)

Any obvious mistakes that I made?

Usually, my question would be more detailed, but as I already said, I am stuck at debugging. On different forums, some people seem to have similar problems, but with different FPGAs or software. What else can I try?

 

My specs:

Host PC: Ubuntu 18.04 LTS

Vivado 2018.2

SDK 2018.2

Mini-ITX-7Z-ASY-G Eva Board with 7z045 SoC

 

Best regards and have a nice weekend!

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luhb
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Registered: ‎01-23-2020

Edit 2:

For anyone having the same problem as me. Here are some things that I changed:

1) In the Vivado block diagram, enable Dual Quad SPI (Parallel 8 bit). This seems to be something the Z100/Z045 SoC needs that Vivado doesn't do automatically.

2) Disable PL with the Switches SW7 (switch 5)

In the meantime, I switched to Z100 because it is possible that something is wrong with my Z045 board. With the same configuration as above, the Z100 didn't get its Cores suspended, but the System Debugger gets stuck at 99%. SDK freezes and you can only continue working when switching off the board. With 1) und 2), "helloworld" is printed into the terminal. Even though this way, I will not be able to work with my PL, the original question is answered and I will mark it as solved.

Also, when downloading the board support package from zedboard.org, I saw that there is a (really nice) documentation for configuring the block diagram in Vivado. Avnet should defininately provide this helpful document in the download section of their product website... I only found it on zedboard.org (which I didn't know belongs to Avnet), same with the complete board definition files. Avnet support couldn't tell me where to find these board definition files and additional documentation. Please improve this, Avnet!

In the additional document there are also other helpful and important steps to mention when creating the block diagram.

View solution in original post

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luhb
Visitor
Visitor
380 Views
Registered: ‎01-23-2020

Edit 2:

For anyone having the same problem as me. Here are some things that I changed:

1) In the Vivado block diagram, enable Dual Quad SPI (Parallel 8 bit). This seems to be something the Z100/Z045 SoC needs that Vivado doesn't do automatically.

2) Disable PL with the Switches SW7 (switch 5)

In the meantime, I switched to Z100 because it is possible that something is wrong with my Z045 board. With the same configuration as above, the Z100 didn't get its Cores suspended, but the System Debugger gets stuck at 99%. SDK freezes and you can only continue working when switching off the board. With 1) und 2), "helloworld" is printed into the terminal. Even though this way, I will not be able to work with my PL, the original question is answered and I will mark it as solved.

Also, when downloading the board support package from zedboard.org, I saw that there is a (really nice) documentation for configuring the block diagram in Vivado. Avnet should defininately provide this helpful document in the download section of their product website... I only found it on zedboard.org (which I didn't know belongs to Avnet), same with the complete board definition files. Avnet support couldn't tell me where to find these board definition files and additional documentation. Please improve this, Avnet!

In the additional document there are also other helpful and important steps to mention when creating the block diagram.

View solution in original post

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