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Visitor
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Registered: ‎05-07-2019

[ZYNQMP] Error when accessing SD Card from a code located in TCM and executed by Cortex R5.

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Hi,

I've maybe encountered a problem in the way the Xilffs library works.

When I try to access SD Card with the Xilffs lib in a code located in TCM and executed by Cortex R5, it doesn't work.

R5 has a local address space to access the TCM, hence when it gives a buffer to the DMA controller of the SD controller, this buffer has an address in the R5 TCM local address space which corresponds to the DDR in the Global address space. To make it work I modified the Xsdps driver, but I wonder if I missed something or if there is a problem in this driver.

Thank you for your response,

Thomas

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Visitor
Visitor
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Registered: ‎05-07-2019

Hi @ibaie,

Thank you for your response,

I found an error in the xsdps.c file, in XSdPs_SetupADMA2DescTbl function using 2017.4 SDK version.

I replaced this code:

InstancePtr->Adma2_DescrTbl[DescNum].Address =
					(u32)((UINTPTR)Buff + (DescNum*XSDPS_DESC_MAX_LENGTH));

 

by this one:

if (Buff < 0x40000) {
	InstancePtr->Adma2_DescrTbl[DescNum].Address =
		(u32)((UINTPTR)Buff + (DescNum*XSDPS_DESC_MAX_LENGTH)) + 0xffe00000;
} else {
	InstancePtr->Adma2_DescrTbl[DescNum].Address =
		(u32)((UINTPTR)Buff + (DescNum*XSDPS_DESC_MAX_LENGTH));
}

 

and this one:

XSdPs_WriteReg(InstancePtr->Config.BaseAddress, XSDPS_ADMA_SAR_OFFSET,
				(u32)(UINTPTR)&(InstancePtr->Adma2_DescrTbl[0]));

by this one:

 

	if (&(InstancePtr->Adma2_DescrTbl[0]) < 0x40000) {
		// Code is in TCM, address need to be shifted because TCM is located in 0x0 from RPU view only
		XSdPs_WriteReg(InstancePtr->Config.BaseAddress, XSDPS_ADMA_SAR_OFFSET,
				(u32)(UINTPTR)&(InstancePtr->Adma2_DescrTbl[0]) + 0xffe00000);
	} else {
		XSdPs_WriteReg(InstancePtr->Config.BaseAddress, XSDPS_ADMA_SAR_OFFSET,
				(u32)(UINTPTR)&(InstancePtr->Adma2_DescrTbl[0]));
	}

When address of the buffer is under 0x40000 (in TCM from RPU view) we shift it to the TCM global address space.

This fix works fine for my example but it might not work if this function is called by the APU.

Regards.

 

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Xilinx Employee
Xilinx Employee
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Registered: ‎10-06-2016
Hi @beckt,
You are right the R5 has a different address space than the global address space in order to map the TCM on 0x0. This in general is not a big deal but if the code is using a DMA engine then the buffers needs to be placed on a common address range.
I'm not that familiar with the library code so it might be good if you can share code snapshots where you found the issue and how did you workaround so we can reproduce on our end and potentially report the issue to the development team.
Regards

Ibai
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Visitor
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Registered: ‎05-07-2019

Hi @ibaie,

Thank you for your response,

I found an error in the xsdps.c file, in XSdPs_SetupADMA2DescTbl function using 2017.4 SDK version.

I replaced this code:

InstancePtr->Adma2_DescrTbl[DescNum].Address =
					(u32)((UINTPTR)Buff + (DescNum*XSDPS_DESC_MAX_LENGTH));

 

by this one:

if (Buff < 0x40000) {
	InstancePtr->Adma2_DescrTbl[DescNum].Address =
		(u32)((UINTPTR)Buff + (DescNum*XSDPS_DESC_MAX_LENGTH)) + 0xffe00000;
} else {
	InstancePtr->Adma2_DescrTbl[DescNum].Address =
		(u32)((UINTPTR)Buff + (DescNum*XSDPS_DESC_MAX_LENGTH));
}

 

and this one:

XSdPs_WriteReg(InstancePtr->Config.BaseAddress, XSDPS_ADMA_SAR_OFFSET,
				(u32)(UINTPTR)&(InstancePtr->Adma2_DescrTbl[0]));

by this one:

 

	if (&(InstancePtr->Adma2_DescrTbl[0]) < 0x40000) {
		// Code is in TCM, address need to be shifted because TCM is located in 0x0 from RPU view only
		XSdPs_WriteReg(InstancePtr->Config.BaseAddress, XSDPS_ADMA_SAR_OFFSET,
				(u32)(UINTPTR)&(InstancePtr->Adma2_DescrTbl[0]) + 0xffe00000);
	} else {
		XSdPs_WriteReg(InstancePtr->Config.BaseAddress, XSDPS_ADMA_SAR_OFFSET,
				(u32)(UINTPTR)&(InstancePtr->Adma2_DescrTbl[0]));
	}

When address of the buffer is under 0x40000 (in TCM from RPU view) we shift it to the TCM global address space.

This fix works fine for my example but it might not work if this function is called by the APU.

Regards.

 

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Xilinx Employee
Xilinx Employee
682 Views
Registered: ‎10-06-2016

Hi @beckt 

Thanks for the details, I just checked the latest code and it seems that the mentioned function implementation has been already changed so not sure how applicable would be the issue nowaday. Anyway I tried to reproduce the issue on my side using 2017.4 running the xilffs_polled_example but I was not able to build it with the data and code section on TCM, there is no space. How did you managed to generate the issue?

You fix seems to be OK but not sure if that's the best way to handle. I mean, from my point of view it would be better to allocate the buffers in a specific section located on a common address space.

Regards


Ibai
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Visitor
Visitor
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Registered: ‎05-07-2019

Hi @ibaie,

I didn't do nothing except putting all sections in TCM. Maybe the fact that my R5 is in lockstep change something.

I know that my solution isn't a real one, but I can't change the buffer address because the buffer is created by the xilffs library and used internally.

Regards.

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Visitor
Visitor
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Registered: ‎12-24-2019

Hello,

I have the very same issue with XilSecure when I try to SHA3 with my .bss in TCM.

I get around this with the "XSecure_Sha3" structure allocated in global TCM or by adding 0xFFE0_0000 to the address provided to the DMA when the SHA3 is "Finished".

Is there any patch to solve this issue ?

Best regards.

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