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gmullin
Visitor
Visitor
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Registered: ‎06-12-2017

Zedboard: No communication with UART 0 when booting with SD Card with baremetal application

Zedboard:

Zynq UART 0 works fine with JTAG

No communication with UART 0 when booting with SD Card with baremetal application

Used Vitis to create a boot image.

The FSBL:  Zed from Xilinx

I can see the expected output from the PL on oscilloscope.

I can see LEDs being turned on by the baremetal application.

The application also writes to UART 0.

But I see no signal with an oscilloscope on UART 0 which is connected to Pmod JA on the Zedboard.

 

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Nikhil_Thapa
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Registered: ‎05-28-2020

Hi @gmullin ,

It could be very helpful to resolve your issue, if you could have given little more information about your design.

Nonetheless, as per my understanding, you might need to check MIO pin configuration. Because, UART and SD card interface use same MIO Banks. 

For more information, you can visit Zedboard User Guide.

 

Thanks and Regards,

nikhil@logictronix.com
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gmullin
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Registered: ‎06-12-2017


March 31 2021

Step 1:
Zynq UART 0 works fine with JTAG
No communication with UART 0 when booting with SD Card with baremetal application
Used Vitis to create a boot image.
The FSBL:  Zed from Xilinx
I can see the expected output from the PL on oscilloscope.
I can see LEDs being turned on by the baremetal application.
The application also writes to UART 0.
But I see no signal with an oscilloscope on UART 0 which is connected to Pmod JA on the Zedboard.


Step 2:


I searched the .mss file in the FSBL application project for uart.

 

/home/gerald/Zedboard_getting_started_zynq_workspace/zed/ps7_cortexa9_0/standalone_ps7_cortexa9_0/bsp/system.mss


I only saw uart_1 and no uart_0

 


BEGIN OS
PARAMETER OS_NAME = standalone
PARAMETER OS_VER = 7.3
PARAMETER PROC_INSTANCE = ps7_cortexa9_0
PARAMETER stdin = ps7_uart_1
PARAMETER stdout = ps7_uart_1
END

 

 

BEGIN DRIVER
PARAMETER DRIVER_NAME = uartps
PARAMETER DRIVER_VER = 3.10
PARAMETER HW_INSTANCE = ps7_uart_1
END

 

Step 3:

I changed all XUARTPS_0 to XUARTPS_1 as follows:

 

 

 

#define UART_DEVICE_ID XPAR_XUARTPS_0_DEVICE_ID

to

#define UART_DEVICE_ID XPAR_XUARTPS_1_DEVICE_ID

 

#define UART_INT_IRQ_ID XPAR_XUARTPS_0_INTR

to

#define UART_INT_IRQ_ID XPAR_XUARTPS_1_INTR

 


Step 4:


In Vivado I modified Zynq and added UART1. I relabeled ports UART0_TX and UART0_RX to UART1_TX and UART1_RX and connected to Zynq UART1.

I modified constraint file (.xdc) with the new labels. (The Zynq is connected to UART by EMIO pins)

 

 


Step 5:

I observed signals being transmitted.


///////////////////////////////////////////////////////////////////////////////

April 1, 2012:


Step 6:

But my program cannot receive.

 


//arch = zynq; split = false; format = BIN
the_ROM_image:
{
[bootloader]/home/gerald/Zedboard_getting_started_zynq_workspace/app_fsbl_boot_components/Debug/app_fsbl_boot_components.elf
/home/gerald/fpga_beginning_2020/prj_b000/design_6_wrapper.bit
/home/gerald/Zedboard_getting_started_zynq_workspace/app_mar31b/Debug/app_mar31b.elf
}

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