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hbucher
Scholar
Scholar
2,501 Views
Registered: ‎03-22-2016

Zybo + JTAG select

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For a long time I have been programming the Zybo with the programming select mode turned to 'JTAG' (callout 21 on PDF)

https://reference.digilentinc.com/_media/zybo:zybo_rm.pdf

With that option I could never do any board debugging because after programming I would always get this error.

 

WARNING: [Labtools 27-3123] The debug hub core was not detected at User Scan Chain 1 or 3.
Resolution: 
1. Make sure the clock connected to the debug hub (dbg_hub) core is a free running clock and is active OR
2. Manually launch hw_server with -e "set xsdb-user-bscan " to detect the debug hub at User Scan Chain of 2 or 4. To determine the user scan chain setting, open the implemented design and use: get_property C_USER_SCAN_CHAIN [get_debug_cores dbg_hub].
WARNING: [Labtools 27-1974] Mismatch between the design programmed into the device xc7z010_1 and the probes file(s) M:/Work/Vivado/project_16/project_16.runs/impl_1/debug_nets.ltx.
The device design has 0 ILA core(s) and 0 VIO core(s). The probes file(s) have 1 ILA core(s) and 0 VIO core(s).
Resolution: 
1. Reprogram device with the correct programming file and associated probes file(s) OR
2. Goto device properties and associate the correct probes file(s) with the programming file already programmed in the device.

Where am I goofing? Isnt' JTAG to be selected when you are programming directly from the SDK (as opposed to booting from QSPI or SD)? Or that means programming from the EXTERNAL JTAG connector (callout 20/22)?

 

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florentw
Moderator
Moderator
4,230 Views
Registered: ‎11-09-2015

Hi @hbucher,

 

This message is common on Zynq. This is because your ILA is using the PS clock and the PS clock is not up.

 

To debug a zynq application, open SDK and launch your application in debug (let it stop a the entry point). This will configure the zynq PS, so your PS clocks will be up.

Then you can program the PL part in vivado and you will see you ILAs.

 

Hope that helps,

 

Florent


Florent
Product Application Engineer - Xilinx Technical Support EMEA
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florentw
Moderator
Moderator
4,231 Views
Registered: ‎11-09-2015

Hi @hbucher,

 

This message is common on Zynq. This is because your ILA is using the PS clock and the PS clock is not up.

 

To debug a zynq application, open SDK and launch your application in debug (let it stop a the entry point). This will configure the zynq PS, so your PS clocks will be up.

Then you can program the PL part in vivado and you will see you ILAs.

 

Hope that helps,

 

Florent


Florent
Product Application Engineer - Xilinx Technical Support EMEA
**~ Don't forget to reply, give kudos, and accept as solution.~**

View solution in original post