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Jain
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Registered: ‎06-30-2020

Zybo Z20 UART loopback mode

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I'm using Vivado & Vitis 2019.1 version and using Zybo z20 board for training serial transceiver.

I want to try to make a local loopback mode of UART like  Zynq-7000 SoC Technical Reference Manual   page 597

I make a RAM(256*8b) and UART will receive and transfer data to RAM like, read data in a top stack of RAM(data will be read in Addr: 0h to fh ), and write it in middle of RAM(data will be written in Adrr: 63h to 76h ). 

Read and write data will be checked by using "debug" function on Vitis soft.

Do you think it possible?. Please, give me some advice or how to build it.

Jain_0-1603340853573.png

Local loopback mode

UART_loopback.PNG

 

 

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stephenm
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Registered: ‎09-12-2007

Looks fine. In fact this is how the driver example code is tested (in loopback):

https://github.com/Xilinx/embeddedsw/blob/master/XilinxProcessorIPLib/drivers/uartps/examples/xuartps_intr_example.c

 

* @file xuartps_intr_example.c
  *
  * This file contains a design example using the XUartPs driver in interrupt
  * mode. It sends data and expects to receive the same data through the device
  * using the local loopback mode.

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stephenm
Moderator
Moderator
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Registered: ‎09-12-2007

Looks fine. In fact this is how the driver example code is tested (in loopback):

https://github.com/Xilinx/embeddedsw/blob/master/XilinxProcessorIPLib/drivers/uartps/examples/xuartps_intr_example.c

 

* @file xuartps_intr_example.c
  *
  * This file contains a design example using the XUartPs driver in interrupt
  * mode. It sends data and expects to receive the same data through the device
  * using the local loopback mode.

View solution in original post

marcb
Moderator
Moderator
277 Views
Registered: ‎05-08-2012

Hi @Jain 

Did the previous post resolve your question? If so, can you mark that as an accepted solution, so that others in the community looking for the same information can find it?

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