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Visitor ayazar
Registered: ‎09-08-2017

Zynq 7000 - SDK Memory View and Cache Relation



During a debug session of a bare metal Zynq application, behavior of debugger was unexpected for us and I want to clarify the situation.


A DMA engine in PL wirtes data to an allocated region in DDR connected to PS constantly and PS reads data from DDR. Since we didn't configure MMU or SCU, we read cached data, not the latest one, in CPU as expected. However, when we looked data using SDK built-in Memory window, we also read cached data. I checked UG585 and other documents but couldn't find a clear answer. How does debugger reach memory? Our expectation was it accesses memory directly but it seems to be accessing from CPU perspective. Once we disable caches in our code, we read recent data from both CPU and Memory window in SDK.


Is this an expected behavior?


Thank you.


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2 Replies
Xilinx Employee
Xilinx Employee
Registered: ‎10-21-2010

Re: Zynq 7000 - SDK Memory View and Cache Relation

Hi Alper,


ARM architecture provides two methods to access memory in debug mode. In the first method, debugger injects LOAD/STR instructions into the CPU core to access memory. Since the CPU core is executing these instructions, memory is accessed via caches. In the second method, debugger uses a dedicated AXI/ABH interface to access physical memory, and no CPU cores/caches are involved.


Which of these two methods the debugger uses to read data depends on the target you've selected in the debug view. When you select a CPU core, debugger uses the CPU cores to access memory. When you select the top level APU target, debugger uses AXI/ABH interface to read memory

Registered: ‎08-16-2018

Re: Zynq 7000 - SDK Memory View and Cache Relation

There are truths, lies and debuggers. Debuggers are useful up to some point, then they aren't because is not the normal operation mode. Incompatible with interrupts and timers, to start with. I prefer having the software self-checking things and writing messages to a debug port. 

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