04-20-2019 07:13 PM
Hardware Platfrom: Zynq7010 MicroZed Development Board
I'm looking at file <xuartps_hw.h> in my BSP and I believe the XUARTPS_MR_STOPMODE_MASK macro is incorrectly defined. According to the Zynq-7000 SoC Techincal Reference Manual (UG585) here in section (Appx. B: Register Details), subsection (UART Controller) and register definition for XUARTPS_MR_OFFSET the bits for the STOPMODE are bits 7:6. Therefore, the mask if I'm not mistaken should be...
#define XUARTPS_MR_STOPMODE_MASK 0x000000C0U
However, the file <xuartps_hw.h> has it defined as 0x000000A0U instead...
Is my assumption here correct or am I crazy?
04-21-2019 08:19 AM
Hah, nice catch. It looks like you're correct. Perhaps you're the first person ever to actually use the 1.5 stop-bits mode - I don't think I've ever seen it used before.
If you leave this thread un-solved for a while, someone from Xilinx should wander along to have a look at it.
04-21-2019 09:34 AM
Hi @scy86dev ,
From the description of register I can see that 7:6 ->11 means reserved, how many stop bits you are expecting?
04-21-2019 05:52 PM - edited 04-21-2019 05:52 PM
I'm just programming for 1 stop bit so this 0xA0 bug or "feature" isn't going to affect me in any way. However, my original question was whether this mask should be 0xC0 instead of 0xA0. This is just a bit mask so what do you mean here by reserved?
04-21-2019 06:12 PM
@abhinayp The problem is if (for example) someone sets the stop mode to 1-bit with:
reg = (reg & ~XUARTPS_MR_STOPMODE_MASK) | XUARTPS_MR_STOPMODE_1_BIT;
If the bottom 8 bits were originally 0x60 (1.5 stop bits, no parity, 8-bit characters) then this changes them to 1.5 stop bits (because it doesn't clear the right bit), even parity, and 8-bit characters. Clearly not what the user was expecting!