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Zynq DDR Power Down in Zynq Technical Reference Manual

Explorer
Posts: 114
Registered: ‎09-11-2012

Zynq DDR Power Down in Zynq Technical Reference Manual

Hi all, 

 

I found an interesting part in Zynq Technical Reference Manual Chapter 10.9.6 saying that the DDR in Zynq could be programmed and powered down by stop the DDR clock when there is no transaction. An example is given on the same page showing how to achieve that by writing various registers to:

 

ddrc.ctrl_reg1[reg_ddrc_selfref_en] = 1
ddrc.DRAM_param_reg3 [reg_ddrc_en_dfi_dram_clk_disable] = 1
while (slcr.DDR_CMD_STA[CMD_Q_NEMPTY] != 0)
while (ddrc.mode_sts_reg[ddrc_reg_operating_mode] != 3)
slcr.DDR_CLK_CTRL[DDR_2XCLKACT] = 0
slcr.DDR_CLK_CTRL[DDR_3XCLKACT] = 0
slcr.DCI_CLK_CTRL[CLKACT] = 0

 

I tried to do that using some C code, writing required value to the above registers. However, the power monitor doesn't show any significant change on DDR power. Is there anything I missed? Does anyone tried that before?

Visitor
Posts: 2
Registered: ‎10-11-2014

Re: Zynq DDR Power Down in Zynq Technical Reference Manual

Hi,

 

I know this thread is now 6 months old but maybe this helps others in the future:

 

You have to unlock the slcr registers first so you can write to slcr.DDR_CLK_CTRL and slcr.DCI_CLK_CTRL. See "SLCR_UNLOCK" in Appendix B of the Zynq TRM for details.

 

By doing this and following the procedure you mentioned I can achieve a measurable loss in power consumption.

 

Greetings,

Michael