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jeffrey.johnson
Voyager
Voyager
1,063 Views
Registered: ‎02-07-2008

Zynq FSBL fails to build, cp: cannot create regular file: Invalid argument

Hi,

I've recently started having a problem with Vitis 2019.2. I've been working with it for a while without having this problem, but now it affects all of my projects.

Without having made any changes to the hardware design or the software, the Zynq FSBL is no longer building. I'm getting this error during the build process:

cp: cannot create regular file (filename here): Invalid argument

That error seems to happen when it tries to build the xilffs library, but I have seen it also occur on the xilsecure library for other projects. I have left out the filename from the error message because it depends on the library that fails. As the library can't build, this causes the Zynq FSBL to not build. On other projects, this also occurs on the PMU application. None of this was occurring before.

I'm using Windows and I think that this has something to do with the operating system, maybe an update or some other software that is now conflicting with Vitis.

If anyone has seen this and has any solutions, please let me know.

Jeff

 

 

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10 Replies
brandnj20fiber
Observer
Observer
1,040 Views
Registered: ‎02-15-2020

I'm still on 2019.1 Vanilla Vivado but anytime I start getting weird things like this on Windows it's a path length issue. Or, the .SDK folder is just borked and I have to blow it away and re-build. I'm not sure what the Vitis equivalent of this is.

P.S. Thanks for posting all that stuff on FPGAdeveloper. I assume thats you. Your source control stuff has been especially helpful to me in the past.

 

 

 

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jeffrey.johnson
Voyager
Voyager
1,033 Views
Registered: ‎02-07-2008

Yes the file length issue was the first thing that I checked - it wasn't the problem in this case. And yes, I write the FPGA Developer blog, although have been out of action for a while.

In the end, I went through all of the programs that were recently installed and one of them was an update to TortoiseGit 2.11. When I uninstalled TortoiseGit, the problem went away and all of my projects are building now.

I tried to rollback to previous versions of TortoiseGit (because I've been using it for years now) but even going back to 2.9 (from 2019), the problem still occurs. So my solution is to just uninstall TortoiseGit altogether and use something else. It's not the first time that TortoiseGit has caused weird issues for me, so I'm not too hung up about it. If anyone is interested to know, GitHub Desktop and SourceTree are two modern and recommended alternatives.

Jeff

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jeffrey.johnson
Voyager
Voyager
901 Views
Registered: ‎02-07-2008

Hi,

Although I have no explanation for this, it turns out that uninstalling TortoiseGit fixed my issue for 2019.2, but the problem is now happening to me on version 2020.1.

I have since done numerous tests on my Windows 10 machine and I find this strange but reproducible behavior:

  • Within the Vitis GUI, if I create a platform from XSA file (see attachment) and then build it, I get the "cp: cannot create regular file" error and Zynq FSBL fails to build.
  • If I do the same as above, but just click on each of the BSPs before building, I get the "cp: cannot create regular file" error but this time it is the Zynq PMU FW that fails to build.
  • From this point, after Vitis has just failed to build, if I then just try rebuilding - it works.

I have also done the same tests on a Ubuntu 16.04 machine, and the errors do NOT occur. Instead, I get a successful build on a the Linux machine the first time around.

This has led me to some forum posts that I think are from people having a similar problem:

https://forums.xilinx.com/t5/Embedded-Development-Tools/VITIS-build-error/td-p/1118411

https://forums.xilinx.com/t5/Embedded-Linux/ZCU111-BSP-makefiles-use-o-and-cause-lots-of-errors-on-windows/td-p/1146091

I would appreciate any help if someone has seen this on their Windows 10 Vitis 2020.1.

Thanks

Jeff

jeffrey.johnson
Voyager
Voyager
894 Views
Registered: ‎02-07-2008

Hi,

More information: This problem happens even when using a pre-built board description provided in Vitis 2020.1. Here are the steps to reproduce the problem:

  1. Open Vitis 2020.1 on a Windows 10 machine, create an empty workspace
  2. Select File->New->Platform Project.
  3. Name the project "test", then click "Next".
  4. Select the pre-build board description "zcu102".
  5. Click "Finish". Vitis will now take a minute to create the platform.
  6. Right click on the "test" platform and select "Build Project".

The build will fail with this error message:

'Finished building libraries'

Failed to generate the platform.
Reason: Failed to build the  zynqmp_fsbl application.
    invoked from within
"::tcf::eval -progress {apply {{msg} {puts $msg}}} {tcf_send_command tcfchan#0 xsdb eval s es {{platform active test; platform generate }}}"
    (procedure "::tcf::send_command" line 4)
    invoked from within
"tcf send_command $::xsdb::curchan xsdb eval s es [list "platform active $PLATFORM_NAME; platform generate $target"]"
    invoked from within
"if { $iswindows == 1 } {    

    set XSDB_PORT [lindex $argv 0]
    set PLATFORM_NAME [lindex $argv 1]
    set arglen [llength $argv]
    set lastind..."
    (file "C:/Xilinx/Vitis/2020.1\scripts\vitis\util\buildplatform.tcl" line 11)

21:18:43 Build Finished (took 4m:35s.914ms)

If you look further up the console, you will find the cause of the failure:

"Running Make include in psu_cortexa53_0/libsrc/xilffs_v4_3/src"

make -C psu_cortexa53_0/libsrc/xilffs_v4_3/src -s include  "SHELL=CMD" "COMPILER=aarch64-none-elf-gcc" "ASSEMBLER=aarch64-none-
elf-as" "ARCHIVER=aarch64-none-elf-ar" "COMPILER_FLAGS=  -O2 -c" "EXTRA_COMPILER_FLAGS=-g -Wall -Wextra -Os -flto -ffat-lto-obj
ects"

make[2]: Entering directory 'C:/projects/Vitis/test/zynqmp_fsbl/zynqmp_fsbl_bsp/psu_cortexa53_0/l
ibsrc/xilffs_v4_3/src'

cp: cannot create regular file `../../../include/ff.h': Invalid argument
cp: cannot create regular file `../../../include/diskio.h': Invalid argument
make[2]: *** [Makefile:53: libxilffs_includes] Error 1
make[1]: *** [Makefile:26: pmake[2]: Leaving directory 'C:/projects/Vitis/axi_eth_v1_wrapper/zynqmp_fsbl/zynqmp_fsbl_bsp/psu_cortexa53_0/lisu_cortexa53_0/lib
src/xilffs_v4_3/src/make.include] Error 2
bsrc/xilffs_v4_3/src'

make: *** [Makefile:30: zynqmp_fsbl_bsp/psu_cortexa53_0/limake[1]: Leaving directory 'C:/projects/Vitis/test/zynqmp_fsbl/zynqmp_fsbl_bsp'
b/libxil.a] Err
or 2

I'd be grateful to anyone who could test this on a Windows 10 machine with Vitis 2020.1 and let me know if they have the same problem. Then I would at least know if it was a Vitis/Windows 10 problem or some kind of software conflict on my particular computer. Thanks!

Jeff

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jeffrey.johnson
Voyager
Voyager
608 Views
Registered: ‎02-07-2008

I've had the time to dig deeper on this issue and this is what I have discovered:

  1. This is an intermittent problem. The build doesn't always fail on the same driver, but always with the same problem (cp cannot create regular file). I can run the build over and over and I get different results.
  2. This problem does not happen when I boot Windows 10 in Safe Mode. This suggests to me that this is a conflict with some other software running on my machine. I have gone through the tedious process of killing processes one by one to determine the problem software, but I didn't find it.
  3. This problem occurs only on my C: (the same drive that Vitis is installed). When creating the Vitis workspace on any other drive, the build works fine. I have swapped my C: with a new SSD, but the problem still occurs, so this is not a hardware problem.

All of that together tells me that this is probably a software conflict, and probably something that not many people are experiencing. I'm just posting this update in the chance that some brilliant person might read it and come up with an idea. For now, I will just move my projects over to another drive and work from there.

Thanks.

Jeff

davidsummers
Contributor
Contributor
396 Views
Registered: ‎05-18-2015

I am having the same issue in Vitis 2020.2 under Windows 10.  Each time I try to build my platform/bsp I get the "cp: cannot create regular file ...  Invalid argument" error.  The error is for a different file each time.   If I build the platform multiple times, it will eventually build successfully.    I started having this problem once I added the lwip library to my application, but that might just be a coincidence.

I did have TortoiseGIT installed.  I uninstalled it, but the issue is still there.

 

Are there any Xilinx employees out there that can comment on this issue?

 

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davidsummers
Contributor
Contributor
350 Views
Registered: ‎05-18-2015

Update:  Just like Jeff, the issue goes away if I create the Vitis workspace on the D:\ drive (Vitis is installed on C:\Xilinx\Vitis\2020.2 ).  In my case, my laptop only has one SSD and I am using a 32G flash drive as D:.  This is not a viable long term solution for me.

I tried booting Windows in safe mode as Jeff suggested, but Vitis would not start in safe mode so I could not test whether this error persists in safe mode.

For me, it seems to be the inclusion of the lwip libraries that breaks Vitis.

The following TCL commands create and build hello world with no errors:

 

 

 

platform create -name ADL_FPGA_TE0802_bd_wrapper -hw zcu102 -arch {64-bit} -fsbl-target {psu_cortexa53_0} 
domain create -name {freertos10_xilinx_psu_cortexa53_0} -display-name {freertos10_xilinx_psu_cortexa53_0} -os {freertos10_xilinx} -proc {psu_cortexa53_0} -runtime {cpp} -arch {64-bit} 
platform generate 
app create -name zynq_te0802 -platform ADL_FPGA_TE0802_bd_wrapper -domain freertos10_xilinx_psu_cortexa53_0 -template {FreeRTOS Hello World}
app build -name zynq_te0802

 

 

 

 

But adding the switch "-support-app {freertos_lwip_echo_server}" to the domain create command causes the "cp: cannot create regular file " error.

This set of commands fails every time on my C drive, but builds just fine on a USB flash drive:

 

 

 

platform create -name ADL_FPGA_TE0802_bd_wrapper -hw zcu102 -arch {64-bit} -fsbl-target {psu_cortexa53_0} 
domain create -name {freertos10_xilinx_psu_cortexa53_0} -display-name {freertos10_xilinx_psu_cortexa53_0} -os {freertos10_xilinx} -proc {psu_cortexa53_0} -runtime {cpp} -arch {64-bit} -support-app {freertos_lwip_echo_server}
platform generate 
app create -name zynq_te0802 -platform ADL_FPGA_TE0802_bd_wrapper -domain freertos10_xilinx_psu_cortexa53_0 -template {FreeRTOS Hello World}
app build -name zynq_te0802

 

 

 

 

The error that I get looks like this (but the name of the source file that caused the error is different each time):

 

 

 

"Running Make include in psu_cortexa53_0/libsrc/zdma_v1_10/src"

"Include files for this library have already been copied."

make -C psu_cortexa53_0/libsrc/zdma_v1_10/src -s include  "SHELL=CMD" "COMPILER=aarch64-none-elf-gcc" "ASSEMBLER=aarch64-none-e
lf-as" "ARCHIVER=aarch64-none-elf-ar" "COMPILER_FLAGS=  -O2 -c" "EXTRA_COMPILER_FLAGS=-g -Wall -Wextra -Os -flto -ffat-lto-obje
cts"

cp: cannot create regular file `../../../include/xsecure_rsa_hw.h': Invalid argument

make[3]: *** [Makefile:51: libxilsecure_includes] Error 1

make[2]: *** [Makefile:41: psu_cortexa53_0/libsrc/xilsecure_v4_3/src/make.include] Error 2

make[1]: *** [Makefile:19: all] Error 2

make[1]: Leaving directory 'C:/LASP_GIT/ADL/sw/zynq/hello_world/ADL_FPGA_TE0802_bd_wrapper/zynqmp_fsbl/zynqmp_fsbl_bsp'

make: *** [Makefile:30: zynqmp_fsbl_bsp/psu_cortexa53_0/lib/libxil.a] Error 2

 

 

 

 

Other things that I have tried to fix this (that all have failed to fix the issue)

  1. complete removal and re-install of Vitis 2020.2
  2. Create my vitis workspace in c:\test to try to reduce the length of the path

 

If I create a new workspace, and then create the freertos lwip echo server app using the "New Application Project" Wizard in the Vitis GUI, then the BSP builds without error.  However, if I make any changes to the BSP (like setting the lwip buffer pool size) then I get the "cp: cannot create regular file ..." error when I attempt to build the platform.

 

The strange thing is that it is always the FSBL that fails to build, and the error is always related to the lwip library.  The lwip library should not even get used by the FSBL.   (I am not making any changes to the default FSBL code).

 

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marcb
Moderator
Moderator
293 Views
Registered: ‎05-08-2012

Hi @davidsummers 


Can you create a new post instead of adding to an older post? This helps to avoid confusion. Even with the same symptoms, they might be different issues.

I wasn't able to reproduce with the XSCT command sequence given using Windows 10 and 2020.2. There were a few changes required because of command argument errors relating to targeting the psu_cortexa53_0 and RTOS. Here are the commands that compiled with no issue.

 

 

platform create -name ADL_FPGA_TE0802_bd_wrapper_2 -hw $xsa -arch {64-bit} -proc {psu_cortexa53_0} 

domain create -name {freertos10_xilinx_psu_cortexa53_2} -display-name {freertos10_xilinx_psu_cortexa53_2} -os {freertos10_xilinx} -proc {psu_cortexr5_0} -runtime {cpp} -support-app {freertos_lwip_echo_server}
platform generate 

app create -name zynq_te0802_2 -platform ADL_FPGA_TE0802_bd_wrapper_2 -domain freertos10_xilinx_psu_cortexa53_2 -template {FreeRTOS Hello World}
app build -name zynq_te0802_2

 

In a new post, can you attach the XSA?

 

 

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jeffrey.johnson
Voyager
Voyager
280 Views
Registered: ‎02-07-2008

Hi @marcb 

Thanks for your input. Actually I think that @davidsummers problem is the same as mine, so I appreciate him adding to this post:

  • We both have the exact same error message
  • We both are using the same version of Vitis (in fact, I experience the problem in both 2020.1 and 2020.2)
  • We both have failure during compilation of the FSBL
  • We both are experiencing intermittent results
  • We both can "fix" the problem by moving our projects to another drive

If you are willing to try to reproduce this problem, please follow the steps that I outlined in my post above using the pre-build board description for the ZCU102. It should not take you very long, and I would very much appreciate it.

 

 

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davidsummers
Contributor
Contributor
260 Views
Registered: ‎05-18-2015

Thank you for the response.  Your version of the TCL commands also causes the error on my computer.  I had to change the $xsa variable to "zcu102" since I am not passing my XSA file to the script.

 

I create a new post as requested:  https://forums.xilinx.com/t5/Embedded-Development-Tools/Zynq-MPSOC-FSBL-fails-to-build-with-error-cp-cannot-create/m-p/1219011 

 

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