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Scholar
Scholar
11,310 Views
Registered: ‎06-10-2008

Zynq FSBL won't read boot.bin from SD card with CD disabled

Hi,

 

I'm using Vivado 2014.4. If I disable the CD and WP pins for SD0 in the Zynq block design, I would expect the exported hardware and then generated FSBL to just read the SD card. But it appears that it needs CD enabled and routed to a MIO pin that's connected to GND. The problem is not in the BOOTROM since the FSBL is started from the uSD card. So my silicon is new enough. Can anyone confirm this? Is Xilinx working to fix this?

 

Maarten

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6 Replies
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Scholar
Scholar
11,305 Views
Registered: ‎06-10-2008

Re: Zynq FSBL won't read boot.bin from SD card with CD disabled

I've already tried to set the bits

 Card_detect_signal_detetction and

 Card_Detect_Test_Level in

 Host_control_Power_control_Block_Gap_Control_Wakeup_control 

but that doesn't work as it hangs the FSBL.

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Visitor
Visitor
11,214 Views
Registered: ‎04-07-2015

Re: Zynq FSBL won't read boot.bin from SD card with CD disabled

I can confirm the same problem with 2014.4

 

--- FSBL Debug Enabled ---

-----------------------------------

 

Xilinx First Stage Boot Loader
Release 2014.4  Apr  7 2015-13:00:28
Devcfg driver initialized
Silicon Version 3.1
Boot mode is SD
SD: rc= 0
disk_initialize: FILE_SYSTEM_INTERFACE_SD
SD: Unable to open file BOOT.BIN: 3
                                   SD_INIT_FAIL
FSBL Status = 0xA009

This Boot Mode Doesn't Support Fallback
In FsblHookFallback function

 

-----------------------

 

 

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Scholar
Scholar
11,202 Views
Registered: ‎09-05-2011

Re: Zynq FSBL won't read boot.bin from SD card with CD disabled

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Visitor
Visitor
11,186 Views
Registered: ‎04-07-2015

Re: Zynq FSBL won't read boot.bin from SD card with CD disabled

… I found the bug in the 2014.4 FSBL code.

 

The default SD clock frequency is 125000000

 

Changing the clock freqency to 25000000 in XSdPs_CfgInitialize will correct the problem. This is a hack to get the

FSBL to work and if the BSP is regenerated it will overwrite the BSP files.

 

 

 

 

---------------------------------------

Xilinx First Stage Boot Loader

Release 2014.4 Apr 8 2015-14:07:23

Devcfg driver initialized

Silicon Version 3.1

Boot mode is SD

SD: rc= 0

XSdPs_Change_ClkFreq: Config.InputClockHz: 125000000 SelFreq=400000

XSdPs_CfgInitialize: XSdPs_Change_ClkFreq: Status=1

SD: Unable to open file BOOT.BIN: 3

                                   SD_INIT_FAIL

FSBL Status = 0xA009

 

This Boot Mode Doesn't Support Fallback

In FsblHookFallback function

----------------------------------------

 

XSdPs_CfgInitialize will fail:

 

Changing xsdps.c Line 165 to:

       Status = XSdPs_Change_ClkFreq(InstancePtr, 25000000);

 

And the FSBL now works.

 

int XSdPs_CfgInitialize(XSdPs *InstancePtr, XSdPs_Config *ConfigPtr,

                               u32 EffectiveAddr)

{

       …

       /*

         * Change the clock frequency to 400 KHz

         */

        

       //Status = XSdPs_Change_ClkFreq(InstancePtr, XSDPS_CLK_400_KHZ);

       // 400000 is too small. The clock change API will fail

       //

       Status = XSdPs_Change_ClkFreq(InstancePtr, 25000000);

       xil_printf("XSdPs_CfgInitialize: XSdPs_Change_ClkFreq: Status=%d \r\n", Status);

      if (Status != XST_SUCCESS) {

               Status = XST_FAILURE;

               goto RETURN_PATH ;

       }

   …

}

------------------------------------------

--- Called by XSdPs_CfgInitialize ---

--- Fails with ClkLoopCnt = 9      ----

------------------------------------------

 

int XSdPs_Change_ClkFreq(XSdPs *InstancePtr, u32 SelFreq)

{

       /*

         * Calculate divisor

         */

       DivCnt = 0x1;

       for(ClkLoopCnt = 0; ClkLoopCnt < XSDPS_CC_MAX_NUM_OF_DIV;

               ClkLoopCnt++) {

               if( ((InstancePtr->Config.InputClockHz)/DivCnt) <= SelFreq) {

                       Divisor = DivCnt/2;

                       Divisor = Divisor << XSDPS_CC_DIV_SHIFT;

                       break;

               }

               DivCnt = DivCnt << 1;

       }

 

       if(ClkLoopCnt == 9) {

 

               /*

                 * No valid divisor found for given frequency

                 */

               xil_printf("XSdPs_Change_ClkFreq: Config.InputClockHz: %d SelFreq=%d \r\n", InstancePtr->Config.InputClockHz, SelFreq);

               Status = XST_FAILURE;

               goto RETURN_PATH;

       }

 

}

 

----------------------------------------------------------

 

Xilinx First Stage Boot Loader
Release 2014.4 Apr 8 2015-14:12:54
Devcfg driver initialized
Silicon Version 3.1
Boot mode is SD
SD: rc= 0
XSdPs_CfgInitialize: XSdPs_Change_ClkFreq: Status=0
SD Init Done
Flash Base Address: 0xE0100000
Reboot status register: 0x60400000
Multiboot Register: 0x0000C000
Image Start Address: 0x00000000
Partition Header Offset:0x00000C80
Partition Count: 4
Partition Number: 1
Header Dump
Image Word Len: 0x0016CFC8
Data Word Len: 0x0016CFC8
Partition Word Len:0x0016CFC8
Load Addr: 0x00000000
Exec Addr: 0x00000000
Partition Start: 0x000065D0
Partition Attr: 0x00000020
Partition Checksum Offset: 0x00000000
Section Count: 0x00000001
Checksum: 0xFFBB2866
Bitstream
In FsblHookBeforeBitstreamDload function
PCAP:StatusReg = 0x40000A30
PCAP:device ready
PCAP:Clear done
Level Shifter Value = 0xA
Devcfg Status register = 0x40000A30
PCAP:Fabric is Initialized done
PCAP register dump:
PCAP CTRL 0xF8007000: 0x4C00E07F
PCAP LOCK 0xF8007004: 0x0000001A
PCAP CONFIG 0xF8007008: 0x00000508
PCAP ISR 0xF800700C: 0x0802000B
PCAP IMR 0xF8007010: 0xFFFFFFFF
PCAP STATUS 0xF8007014: 0x00001A30
PCAP DMA SRC ADDR 0xF8007018: 0x00100001
PCAP DMA DEST ADDR 0xF800701C: 0xFFFFFFFF
PCAP DMA SRC LEN 0xF8007020: 0x0016CFC8
PCAP DMA DEST LEN 0xF8007024: 0x0016CFC8
PCAP ROM SHADOW CTRL 0xF8007028: 0xFFFFFFFF
PCAP MBOOT 0xF800702C: 0x0000C000
PCAP SW ID 0xF8007030: 0x00000000
PCAP UNLOCK 0xF8007034: 0x757BDF0D
PCAP MCTRL 0xF8007080: 0x30800100

DMA Done !

FPGA Done !
In FsblHookAfterBitstreamDload function
Partition Number: 2
Header Dump
Image Word Len: 0x00014871
Data Word Len: 0x00014871
Partition Word Len:0x00014871
Load Addr: 0x04000000
Exec Addr: 0x04000000
Partition Start: 0x001735A0
Partition Attr: 0x00000010
Partition Checksum Offset: 0x00000000
Section Count: 0x00000001
Checksum: 0xF7E4EE9B
Application
Partition Number: 3
Header Dump
Image Word Len: 0x0000072F
Data Word Len: 0x0000072F
Partition Word Len:0x0000072F
Load Addr: 0x00000000
Exec Addr: 0x00000000
Partition Start: 0x00A80000
Partition Attr: 0x00000010
Partition Checksum Offset: 0x00000000
Section Count: 0x00000001
Checksum: 0xFF57E7F1
Application
Handoff Address: 0x04000000
In FsblHookBeforeHandoff function
SUCCESSFUL_HANDOFF
FSBL Status = 0x1

-------------------------------------------

 

Highlighted
Scholar
Scholar
11,175 Views
Registered: ‎06-10-2008

Re: Zynq FSBL won't read boot.bin from SD card with CD disabled

I kind of fail to see how this is related to disabling CD and WP pins. So I very much doubt this is 'the bug'.

 

Furthermore, I would expect this 125MHz to come from the Zynq PS settings in the Block Design. I think you should solve it there. Though it is still unclear to me where I can find the normal operating frequency for the SD interface. The UG585 seems to indicate 50MHz max. for MIO and 25MHz for EMIO. And the weird thing is I have found other designs using 100MHz as well that also seem to work.

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Visitor
Visitor
11,165 Views
Registered: ‎04-07-2015

Re: Zynq FSBL won't read boot.bin from SD card with CD disabled

The CD or WP pins in this case are not the problem.The issue is the default setting because the SD card initialization code in the FSBL fails to calculate the initial SD clock frequency. If the setting is 100Mhz  the frequency calculation passes so this explains why 100Mhz works. This can be seen from clock devisor loop in the FSBL clock XSdPs_Change_ClkFreq code. Since the freqency for SD cards can be 0-25Mhz , up to 52Mhz for UHC, so why fail on a frequency of 125Mhz? The unexpected behaviour would definitely classify this as a major bug and given the clarity of the documention not the only bug.

 

 

 

 

 

 

 

 

 

 

 

 

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