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Visitor sosod
Visitor
3,444 Views
Registered: ‎05-06-2014

Zynq: SCU

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Hello,

 

I have questions about the scu on zynq.

 

1. About the SCU_Control_Register (0xF8F00000)

I have read the Zynq TRM and the ARM Cortex A9 MPCore TRM documentations. But those two documents don't say the same thing about enabling the SCU and the value of the first bit of the register

In the Zynq TRM, it is said that the first bit is at 0 by default and that SCU is disable. To enable SCU, this bit must be 1.

In the ARM Cortex A9 MPCore TRM, it is the opposit: the first bit is at 1 by default and that SCU is disable. To enable SCU, this bit must be 0.

Which one should I trust ?

 

2. I have read that SCU is responsible for cache coherency and interconnect arbitration. What happens if I disable the SCU? How is the arbitration done and will the address filtering still working?

 

Thanks

 

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Moderator
Moderator
4,703 Views
Registered: ‎04-17-2011

Re: Zynq: SCU

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There is no difference. I hope you are checking bit SCU_enable 

In Zynq TRM:

SCU_enable 0 rw 0x0

1 = SCU enable.
0 = SCU disable. This is the default setting

 

In ARM TRM:

http://infocenter.arm.com/help/topic/com.arm.doc.ddi0407g/DDI0407G_cortex_a9_mpcore_r3p0_trm.pdf (Page 2-5)

[0] SCU enable

1 = SCU enable.
0 = SCU disable. This is the default setting.

 

The SCU block connects the two Cortex-A9 processors to the memory subsystem and contains the
intelligence to manage the data cache coherency between the two processors and the L2 cache. This
block is responsible for managing the interconnect arbitration, communication, cache and system
memory transfers, and cache coherence for the Cortex-A9 processors.

Regards,
Debraj
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Moderator
Moderator
4,704 Views
Registered: ‎04-17-2011

Re: Zynq: SCU

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There is no difference. I hope you are checking bit SCU_enable 

In Zynq TRM:

SCU_enable 0 rw 0x0

1 = SCU enable.
0 = SCU disable. This is the default setting

 

In ARM TRM:

http://infocenter.arm.com/help/topic/com.arm.doc.ddi0407g/DDI0407G_cortex_a9_mpcore_r3p0_trm.pdf (Page 2-5)

[0] SCU enable

1 = SCU enable.
0 = SCU disable. This is the default setting.

 

The SCU block connects the two Cortex-A9 processors to the memory subsystem and contains the
intelligence to manage the data cache coherency between the two processors and the L2 cache. This
block is responsible for managing the interconnect arbitration, communication, cache and system
memory transfers, and cache coherence for the Cortex-A9 processors.

Regards,
Debraj
----------------------------------------------------------------------------------------------
Kindly note- Please mark the Answer as "Accept as solution" if information provided is helpful.

Give Kudos to a post which you think is helpful and reply oriented.
----------------------------------------------------------------------------------------------
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Visitor sosod
Visitor
3,405 Views
Registered: ‎05-06-2014

Re: Zynq: SCU

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Thank you for your reply.

It seems ARM has changed his manual since the Zynq exists. And I was looking at the release r4p1 in which it is different. I will follow what the Zynq TRM says.

 

 

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