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Contributor
Contributor
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Registered: ‎05-14-2018

Zynq UltraScale+ Processing System DDR Burst Length

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I get an error when trying to attach the SDK to the target via JTAG. The error is the same as detialed in this Answers Record:

https://www.xilinx.com/support/answers/67623.html

The solution is to use the "Zynq UltraScale+ Processing System GUI" to modify the "PS DDR Burst Length" to be 8 instead of the default of 16. I'm using Vivado 2018.3 and VCU TRD design (rdf0428) on the ZCU106 dev board and I have not been able to find any option to change the DDR burst length.

How can the burst length be changed?

Screenshot from 2019-06-21 16-47-01.png

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517 Views
Registered: ‎04-23-2019
Running FSBL first then my app fixed the problem.

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Xilinx Employee
Xilinx Employee
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Registered: ‎09-01-2014
That setting is removed in the latest version.
Please check the following SODIMM issue for your ZCU106 board. I think you would need to run FSBL first, then run VCU TRD example.
https://www.xilinx.com/support/answers/71961.html
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518 Views
Registered: ‎04-23-2019
Running FSBL first then my app fixed the problem.

View solution in original post

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