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movax
Explorer
Explorer
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Registered: ‎11-09-2013

ZynqMP FSBL Build Failure with FSBL_DEBUG_INFO

Hi there —

Trying to build ZynqMP FSBL using SDK 2019.1 and running into some issues with I think are probably ELF size / code size related as it won't fit into OCM anymore:

aarch64-none-elf-gcc -n -Wl,-T -Wl,../src/lscript.ld -LC:/dev/<snip>/psu_cortexa53_0/lib -o "fsbl.elf"  ./src/psu_init.o ./src/xfsbl_authentication.o ./src/xfsbl_board.o ./src/xfsbl_bs.o ./src/xfsbl_csu_dma.o ./src/xfsbl_ddr_init.o ./src/xfsbl_dfu_util.o ./src/xfsbl_exit.o ./src/xfsbl_handoff.o ./src/xfsbl_hooks.o ./src/xfsbl_image_header.o ./src/xfsbl_initialization.o ./src/xfsbl_main.o ./src/xfsbl_misc.o ./src/xfsbl_misc_drivers.o ./src/xfsbl_nand.o ./src/xfsbl_partition_load.o ./src/xfsbl_plpartition_valid.o ./src/xfsbl_qspi.o ./src/xfsbl_rsa_sha.o ./src/xfsbl_sd.o ./src/xfsbl_translation_table.o ./src/xfsbl_usb.o   -Wl,--start-group,-lxil,-lgcc,-lc,--end-group -Wl,--start-group,-lxilsecure,-lxil,-lgcc,-lc,--end-group -Wl,--start-group,-lxilffs,-lxil,-lgcc,-lc,--end-group -Wl,--start-group,-lxilpm,-lxil,-lgcc,-lc,--end-group
c:/xilinx/sdk/2019.1/gnu/aarch64/nt/aarch64-none/bin/../lib/gcc/aarch64-none-elf/8.2.0/../../../../aarch64-none-elf/bin/ld.exe: address 0xfffe9ec8 of fsbl.elf section `.dup_data' is not within region `psu_ocm_ram_0_S_AXI_BASEADDR'
c:/xilinx/sdk/2019.1/gnu/aarch64/nt/aarch64-none/bin/../lib/gcc/aarch64-none-elf/8.2.0/../../../../aarch64-none-elf/bin/ld.exe: address 0xfffe9ec8 of fsbl.elf section `.dup_data' is not within region `psu_ocm_ram_0_S_AXI_BASEADDR'
c:/xilinx/sdk/2019.1/gnu/aarch64/nt/aarch64-none/bin/../lib/gcc/aarch64-none-elf/8.2.0/../../../../aarch64-none-elf/bin/ld.exe: address 0xfffe9ec8 of fsbl.elf section `.dup_data' is not within region `psu_ocm_ram_0_S_AXI_BASEADDR'
c:/xilinx/sdk/2019.1/gnu/aarch64/nt/aarch64-none/bin/../lib/gcc/aarch64-none-elf/8.2.0/../../../../aarch64-none-elf/bin/ld.exe: address 0xfffe9ec8 of fsbl.elf section `.dup_data' is not within region `psu_ocm_ram_0_S_AXI_BASEADDR'
c:/xilinx/sdk/2019.1/gnu/aarch64/nt/aarch64-none/bin/../lib/gcc/aarch64-none-elf/8.2.0/../../../../aarch64-none-elf/bin/ld.exe: address 0xfffe9ec8 of fsbl.elf section `.dup_data' is not within region `psu_ocm_ram_0_S_AXI_BASEADDR'
c:/xilinx/sdk/2019.1/gnu/aarch64/nt/aarch64-none/bin/../lib/gcc/aarch64-none-elf/8.2.0/../../../../aarch64-none-elf/bin/ld.exe: section .handoff_params VMA [00000000fffe9e00,00000000fffe9e87] overlaps section .dup_data VMA [00000000fffe8200,00000000fffe9ec7]
collect2.exe: error: ld returned 1 exit status
make: *** [makefile:38: fsbl.elf] Error 1

With FSBL_DEBUG_INFO not defined, the build succeeds. Turning on optimize for size doesn't seem to help; do I need to build in a non-Debug configuration? I'm mostly aiming to get up and running here into U-Boot and Linux and don't see a need to swim around the FSBL and debug just yet. 

Can upload my HDF / HPS / other files as needed.

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13 Replies
stephenm
Xilinx Employee
Xilinx Employee
2,718 Views
Registered: ‎09-12-2007

Do you need to debug the FSBL? Are you seeing an issue here (other than the size)

 

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movax
Explorer
Explorer
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Registered: ‎11-09-2013

Hi Stephen —

Nope, I don't need to debug the FSBL (yet, knock on wood, don't want to be in a place where I am stepping through the FSBL with a SmartLynq), just wanted the verbose output printed to console as I work to bring up a new board and debug issues with handing off to U-Boot.

I take it from your comment though that the issue is in fact that the FSBL binary w/ debug support being too large to fit in the OCM? Can I do any of the tricks from the Zynq-7000 FSBL where I can strip out ps*_init tables for silicon revisions I know I will never use (ES, early revs, etc.)?

Thanks!

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stephenm
Xilinx Employee
Xilinx Employee
2,713 Views
Registered: ‎09-12-2007

The fsbl_debug_info will enable the prints in the code. This is useful if the fsbl isn't working, but in you don't need this. 

Without this you will just see basic info about the fsbl. 

 

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movax
Explorer
Explorer
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Registered: ‎11-09-2013

Stephen —

Is there an easy fix or workaround if I want to use FSBL_DEBUG_INFO to enable the prints in code, but don't need to "actually" debug (i.e. connect via JTAG)?

I'm not sure if your comment is suggesting that I try to get my system and up and running without the FSBL_DEBUG_INFO additional info; I found the partition status useful when I was building an older version of the FSBL in trying to figure out if I had the partitions in the right order / check if trusted firmware was executing / other aspects.

 

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glena
Moderator
Moderator
2,698 Views
Registered: ‎03-19-2014

You can look at the FSBL build options here

You can remove the sections you are not using, NAND boot, Partial bitstream, etc.   This will reduce your FSBL image size.

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movax
Explorer
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Registered: ‎11-09-2013

If I could read, I would be dangerous. I must have glossed over those on the wiki (great addition and documentation resource, by the way!). 

I'll give those options a try tonight and check back in! Reasonably certain that on my Ultra96, I can strip out several of those section but on the ZCU102, I may have to be a little bit more selective.

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movax
Explorer
Explorer
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Registered: ‎11-09-2013

I was still unable to build after disabling big chunks of the FSBL, but the Wiki page clued me in that I might have missed some options in the BSP generation, like "zynqmp_fsbl_bsp", which I have set to True.

I did a plain-text search in the Workspace...what does this option do exactly? Where is it consumed?

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glena
Moderator
Moderator
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Registered: ‎03-19-2014

You should find the zynq_fsbl_bsp paramter set in the system.mss file.   This flag enables optimization in the BSP

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movax
Explorer
Explorer
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Registered: ‎11-09-2013

Yep, I set it and I can now build the FSBL and it fits without an issue; I was more curious about what it is actually doing under the hood. Is it setting compiler options for the BSP (-ffat-lto-objects, -Os)?

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tim_severance
Scholar
Scholar
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Registered: ‎03-03-2017

I am experiencing this same exact problem trying to compile an FSBL for the ZCU104 Zynq UltraScale+ in Vivado/Vitis 2019.2.   Any help getting this resolved would be appreciated.   

 

vitis_errors.png

 

Thanks

Tim

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clutch12
Explorer
Explorer
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Registered: ‎06-05-2014

I don't think the a53 gets OCM. If you want to run/debug/or get printfs you can run out of one of the R5s. Or, you could change your hardware design to give the A53 more OCM memory.

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tim_severance
Scholar
Scholar
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Registered: ‎03-03-2017

@clutch12 ,

   Thanks for the quick response.  I am pretty new to the Zynq architecture.      
   In my block design I selected an MPSoC solely.   Do you know if this corresponds to an a53?   For a simple Hello World should I have chosen a different Zynq sub-category?

Thanks.  
Tim

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clutch12
Explorer
Explorer
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Registered: ‎06-05-2014

@tim_severance yep, just the one block has all the processors. Can you try these steps and see if they work?

https://xilinx-wiki.atlassian.net/wiki/spaces/A/pages/18842019/Zynq+UltraScale+FSBL#ZynqUltraScale+FSBL-HowtocreateFSBLfromVitis?

Thinking about it more something seems off on the platform generation you have in vitis. But, the above steps should work.

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