12-24-2020 04:46 PM
Hi,
I'm trying to get the reset functionality work on a Zynqmp Ultra96+ rev2 board.
The goal is to have (part of) the board reset on a watchdog timeout.
I'm able to trigger a watchdog reset on both APU and RPU, but the board inevitably ends up in a perpetual reset state:
xsdb% targets
1 PS TAP
2 PMU
3 PL
5* PSU
6 RPU (Reset)
7 Cortex-R5 #0 (RPU Reset)
8 Cortex-R5 #1 (RPU Reset)
9 APU (L2 Cache Reset)
10 Cortex-A53 #0 (APU Reset)
11 Cortex-A53 #1 (APU Reset)
12 Cortex-A53 #2 (APU Reset)
13 Cortex-A53 #3 (APU Reset)
The PMU did its job resetting everything, but doesn't bring the system back to life.
Some facts:
xsdb% targets
1 PS TAP
2 PMU
3 PL
5* PSU
6 RPU (Reset)
7 Cortex-R5 #0 (RPU Reset)
8 Cortex-R5 #1 (RPU Reset)
9 APU
10 Cortex-A53 #0 (Reset Catch, EL3(S)/A64)
11 Cortex-A53 #1 (Reset)
12 Cortex-A53 #2 (Reset)
13 Cortex-A53 #3 (Reset)
and I can get out of reset with a 'con' (FSBL will run again fine).
Any help is greatly welcome, as the reset is a must-have for us.