i'm doing an IP block in Verilog ,while i pull up a pin in ISE verilog project , it works (add a pull up statement in UCF file), but then i make my own IP block with using the XPS Create or import peripheral function , turn out this pin does not really pull up, it pull high!!!! i did NOT make any change !!!!
found some information about using wrapper to pull pin up in EDK , but i don't understand how , anyone can share more details?