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Visitor
Visitor
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Registered: ‎12-14-2012

about the IO standard in Xilinx UCF settings.

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thank you for your attention and time.

the project i'm doing needs a 1.8V output , i'v changed my UCF file , define this output pin as "LVCMOS 18" ( also have checked the IO plan ahead software,ensure they are setting properly . )

but when i use the oscilloscope to measure the output , it's still 3.3V ,so i wonder is there any default settings i didn't notice, or has some tricks  about the "LVCMOS 18". accorind to the information i got from internet , the "LVCMOS 18" 's peak voltage is 1.8V , so it should work.

PS:i've pull up all the unused pin , is this the reason?

thanks.

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Teacher
Teacher
5,523 Views
Registered: ‎11-14-2011

Re: about the IO standard in Xilinx UCF settings.

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The settings in your UCF tell the tools what sort of buffer to instantiate. They do not control the physical voltage input/output.

 

So, the question to ask is, what is the Vcco for the Bank in question connected to? If the Vcco for that Bank is hardwired to 3.3V, then it is logical to expect the voltage for those signals to be at that level.

 

Regards,

 

Howard

 

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"That which we must learn to do, we learn by doing." - Aristotle

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Teacher
Teacher
5,524 Views
Registered: ‎11-14-2011

Re: about the IO standard in Xilinx UCF settings.

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The settings in your UCF tell the tools what sort of buffer to instantiate. They do not control the physical voltage input/output.

 

So, the question to ask is, what is the Vcco for the Bank in question connected to? If the Vcco for that Bank is hardwired to 3.3V, then it is logical to expect the voltage for those signals to be at that level.

 

Regards,

 

Howard

 

----------
"That which we must learn to do, we learn by doing." - Aristotle

View solution in original post

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Visitor
Visitor
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Registered: ‎12-14-2012

Re: about the IO standard in Xilinx UCF settings.

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thanks.

actually,i found a similar question in Xilinx Forum , the solution is to connect a same level voltage to the board which exactly you mean. guess should do some research before asking .

but the output is still 3.3v after i connect a 1.8V externel power source to the VCCO ,anyway , thank you for the reply.

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Teacher
Teacher
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Registered: ‎11-14-2011

Re: about the IO standard in Xilinx UCF settings.

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but the output is still 3.3v after i connect a 1.8V externel power source to the VCCO ,anyway

I don't understand how this is even physically possible.

 

 

What do you mean by "external power source"? How is the voltage applied to the device pins? Has the previously applied 3.3V been permanently removed?

 

Are all of the Vcco for that particular bank now connected to 1.8V? Any external pullups on the pin?

 

The only way that a Bank can drive a 3.3V output is if the Vcco is connected to that level.

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"That which we must learn to do, we learn by doing." - Aristotle
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Visitor
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Registered: ‎12-14-2012

Re: about the IO standard in Xilinx UCF settings.

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a jumper was connected the board with that output pin , i didn't pull it off .

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