cancel
Showing results for 
Search instead for 
Did you mean: 
4,371 Views
Registered: ‎05-02-2014

address decoding in AXI4

Jump to solution

Hi,

          How address decoding is done in interconnect in case of burst transaction? Master issues only start address..so should interconnect store the start  address and decode for successive transfers in burst based on this address ?? I am not understanding..please somebody explain.

0 Kudos
1 Solution

Accepted Solutions
Highlighted
Xilinx Employee
Xilinx Employee
5,655 Views
Registered: ‎06-14-2012

Re: address decoding in AXI4

Jump to solution

Yes thats right.AXI Interconnect has the address decoding logic which takes care of this.

For example:burst transactions can be split into multiple transactions if the maximum burst length would otherwise be
exceeded.

 

You can refer to AXI reference guide. Hope this helps.

http://www.xilinx.com/support/documentation/ip_documentation/ug761_axi_reference_guide.pdf

 

 

Regards

Sikta

View solution in original post

0 Kudos
5 Replies
Highlighted
Xilinx Employee
Xilinx Employee
4,364 Views
Registered: ‎08-02-2011

Re: address decoding in AXI4

Jump to solution
The master issues the start address, burst type, burst size, and burst length which a slave can use to obtain the proper data/addresses.
www.xilinx.com
0 Kudos
Highlighted
Xilinx Employee
Xilinx Employee
4,346 Views
Registered: ‎06-14-2012

Re: address decoding in AXI4

Jump to solution

The AXI protocol is burst-based. The master begins each burst by driving control information and the address of
the first byte in the transaction to the slave. As the burst progresses, the slave must calculate the addresses of
subsequent transfers in the burst.A burst must not cross a 4KB address boundary.

 

This is again determined by other parameters like burst length, burst size, burst address and burst type.

You can find more information on the address structuring in AMBA AXI spec.

0 Kudos
Highlighted
4,339 Views
Registered: ‎05-02-2014

Re: address decoding in AXI4

Jump to solution

Thanks for the reply..i got the point that slave has to calculate the address of subsequent transfers in a burst..

   but how these transfers reach master interface(slave side in interconnect)  from one master? My assumption is Interconnect should  have some registers to store the burst start address,because address required to select the slave if there is more than one.. am i right?? correct me if iam wrong.

 

0 Kudos
Highlighted
Xilinx Employee
Xilinx Employee
5,656 Views
Registered: ‎06-14-2012

Re: address decoding in AXI4

Jump to solution

Yes thats right.AXI Interconnect has the address decoding logic which takes care of this.

For example:burst transactions can be split into multiple transactions if the maximum burst length would otherwise be
exceeded.

 

You can refer to AXI reference guide. Hope this helps.

http://www.xilinx.com/support/documentation/ip_documentation/ug761_axi_reference_guide.pdf

 

 

Regards

Sikta

View solution in original post

0 Kudos
Highlighted
4,324 Views
Registered: ‎05-02-2014

Re: address decoding in AXI4

Jump to solution
Thanks Sikta for the help. The link is good..I will go through it.

Regars,
Guruhegde
0 Kudos