05-08-2014 01:28 PM
Using the AXI timer/counter block. I did the "Open IP example Design" from Vivado 2014.1 this created a nice project with a working simulation testbench.
I'm wodering if there is a way to set the registers described in pg079 from the testbench?
05-12-2014 10:57 PM
Is this IP driven by a processor? If yes, you need to write a software code using the drivers we provide.
The code will be compiled into an ELF that will be loaded into BRAM's.
During the simulation the processor will run the instructions included in the ELF.
05-12-2014 11:55 PM
These drivers are nostly written by the driver thats available in EDK install dir provided by Xilinx.
You can also write these registers from your C/C++ application in SDK. Few examples in C are already provided.
Please have a look at the following dir.
You can directly include them in your SDK project and build your elf to integrate in your simulation.
05-13-2014 04:19 AM