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Visitor
Visitor
2,905 Views
Registered: ‎05-08-2014

axi testbench with register access

Hi,

 

Using the AXI timer/counter block. I did the "Open IP example Design" from Vivado 2014.1 this created a nice project with a working simulation testbench.

 

I'm wodering if there is a way to set the registers described in pg079 from the testbench?

 

thanks,

Paul

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Xilinx Employee
Xilinx Employee
2,865 Views
Registered: ‎08-02-2007

Re: axi testbench with register access

Hi,

 

Is this IP driven by a processor? If yes, you need to write a software code using the drivers we provide.

 

The code will be compiled into an ELF that will be loaded into BRAM's.

 

During the simulation the processor will run the instructions included in the ELF.

 

--Hem

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Xilinx Employee
Xilinx Employee
2,863 Views
Registered: ‎06-14-2012

Re: axi testbench with register access

These drivers are nostly written by the driver thats available in EDK install dir provided by Xilinx.

You can also write these registers from your C/C++ application in SDK. Few examples in C  are already provided.

Please have a look at the following dir.

C:\Xilinx\14.7\ISE_DS\EDK\sw\XilinxProcessorIPLib\drivers\tmrctr_v2_05_a\examples

 

You can directly include them in your SDK project and build your elf to integrate in your simulation.

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Scholar
Scholar
2,858 Views
Registered: ‎09-05-2011

Re: axi testbench with register access

Yes!

You can edit the test-bench provided in the AXI Timer example design to set the registers.

Specifically, which registers are you looking for?
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