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6,659 Views
Registered: ‎04-03-2014

bidirectional three state IOBUF (not differential)

I am facing with this problem working with XPS.

I would like to have a three state differential buffer to implement the input/output port of a three wire SPI.

In the IP catalog from XPS it's possible to implement just differential buffer "IOBUFDS/IBUFDS/OBUFDS".

Do you have a suggestion how to build up a bidirectional (three state) single ended IOBUF?

Have I to write my own vhdl file? In this case which is the best (and the fastest) way to make a custom IP core and inport it in XPS?

 

Best regards

 

Giuseppe

Giuseppe Gottardo
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5 Replies
Scholar stephenm
Scholar
6,655 Views
Registered: ‎05-06-2012

Re: bidirectional three state IOBUF (not differential)

You can use the CIP in EDK. In the GUI, select "Import Existing Peripheral", Next, select a location where you want to IP to be created, Next, Name the IP the same as your HDL entity, Next, select HDL sources, Next, select browse to your HDL sources, Next, Add files, and add your HDL code, deselect bus interface, Next, deselect and configure interrupts, Next, Next Finish

 

Your IP will be in the IP catalog

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6,638 Views
Registered: ‎04-03-2014

Re: bidirectional three state IOBUF (not differential)

Dear Stephenm,

 

I tried your solution: I used as VHDL file the CELL IOBUF attached (primitives of Xilinx).

I am facing this problem: I created the new Ipcore with xps and after I made sysntesis and implementation in PlanAhead.

There is an error in the netlist generation because of the generation of the wrapper file in xps.

Infact the wrapper file created has these ports:

 

    port (
      O : out std_logic;
      I : in std_logic;
      T : in std_logic;
      IO_I : in std_logic;
      IO_O : out std_logic;
      IO_T : out std_logic
    );

 

whereas my vhdl file (attached) has just these ports:

 

  port(
    O  : out   std_ulogic;
    IO : inout std_ulogic;
    I  : in    std_ulogic;
    T  : in    std_ulogic
    );

 

It seems like there is a translation of ports at netlist level but after the compiler in xps launches an error saying

 


ERROR:HDLCompiler:1156 - "C:\Xilinx\Projects\sysgen_project\project_2\project_2.srcs\sources_1\edk\system_VC707\hdl\system_VC707_iobuf_se_0_wrapper.vhd" Line 40: Formal port <IO_I> does not exist in entity <iobuf_se>.  Please compare the definition of block <iobuf_se> to its component declaration and its instantion to detect the mismatch.
ERROR:HDLCompiler:1156 - "C:\Xilinx\Projects\sysgen_project\project_2\project_2.srcs\sources_1\edk\system_VC707\hdl\system_VC707_iobuf_se_0_wrapper.vhd" Line 41: Formal port <IO_O> does not exist in entity <iobuf_se>.  Please compare the definition of block <iobuf_se> to its component declaration and its instantion to detect the mismatch.
ERROR:HDLCompiler:1156 - "C:\Xilinx\Projects\sysgen_project\project_2\project_2.srcs\sources_1\edk\system_VC707\hdl\system_VC707_iobuf_se_0_wrapper.vhd" Line 42: Formal port <IO_T> does not exist in entity <iobuf_se>.  Please compare the definition of block <iobuf_se> to its component declaration and its instantion to detect the mismatch.
ERROR:EDK:546 - Aborting XST flow execution!

ERROR:EDK:4207 - TRI_I sub-property is not present on tri-state port IO. MPD must not contain port with name IO_I
ERROR:EDK:4208 - TRI_O sub-property is not present on tri-state port IO. MPD must not contain port with name IO_O
ERROR:EDK:4209 - TRI_T sub-property is not present on tri-state port IO. MPD must not contain port with name IO_T

Could you please help me to solve this mismatch?

Thanks in advance for your assistance.

 

Best regards

 

Giuseppe

 

Giuseppe Gottardo
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6,625 Views
Registered: ‎04-03-2014

Re: bidirectional three state IOBUF (not differential)

Looking in the forum I read this post.

Basically I am using axi_spi IP in XPS to interface a doughter card out from a VC707.

I need a 3 wire SPI but the SPI IP core is a normal 4 wire SPI.

I tried connecting a custum IOBUF single ended (an IP core wrote by me myself) in order to convert the four-wire (MOSI, MISO , SCK, SS) to (MOSI/MISO , SCK, SS). Basically I thought to use a three state buffer to manage MOSI and MISO having a single bidirectional IO pin.

 

After reading this guide at pag 68, I understood that the generation of bidirectional IOBUF is automatcally managed by the netlist generation.

So I was thinking about IP core of SPI in XPS. Its code for the port MOSI in MPD is:

 

PORT MOSI = "", TRI_O = MOSI_O, TRI_T = MOSI_T, DIR = IO, TRI_I = MOSI_I, THREE_STATE = TRUE, PERMIT = BASE_USER, DESC = 'Master Out Slave In', IO_IF = spi_0, IO_IS = data_in

 

From my understandig the IP CORE of SPI present in XPS has already bidirectional MOSI and MISO.

Is it true?

How can I use this IP core as a three-wire SPI instead of a four-wire SPI?
Have I to write and build my own SPI three-wire block?

 

Best regards

 

Giuseppe Gottardo
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Scholar stephenm
Scholar
6,617 Views
Registered: ‎05-06-2012

Re: bidirectional three state IOBUF (not differential)

Yes, you will need to modify the MPD file as seen in UG642.

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6,612 Views
Registered: ‎04-03-2014

Re: bidirectional three state IOBUF (not differential)

Yesterday I came to this solution, I created a new IP core to connect signals coming from SPI IP core and with a bidirectional SDIO pin.Could you please check this file IP core (please find attached)? At the moment I am trying bitgen but I have some other problem with the software and I would like at least exclude an error in the XPS project so I can concentrate more on the software in SDK. Thanks again Best regards Giuseppe

Giuseppe Gottardo
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