UPGRADE YOUR BROWSER

We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

cancel
Showing results for 
Search instead for 
Did you mean: 
Visitor ctbctb
Visitor
5,168 Views
Registered: ‎04-08-2012

can't telnet to ML507 (I used TEMAC and chose SGMII )

Hi , I'm a novice in EDK, I use BSB to build a project with TEMAC, and I also added some other necessary Core to it (such as Timer ,DDR2 , Interrupt and Uart ) ,I configured them as the guide PDF said ,which I downloaded form the Xilinx website(ml505_std_ip_pcore_addition.pdf), as I set all the core as the example project which I downloaded form the Xilinx website did , I generated the bitstream , export to SDK and  build the BSPs  successfully , I use the lwip_echo_server which is the one of  the SDK example application , It run well ,and can detecte the PHY(88E1111 marvell) , the out put through Uart is OK , but I can't  telnet it form my PC with CMD command telnet 192.168.1.10 7(the OS of my PC is Win7) ,I don't konw why it doesn't work , ererything seems right, did I miss some important steps????  I think maybe there is something  wrong with my ucf ,the constriants of SGMII, I attach my mhs and ucf ,can anybody can help me ?? I worked on almost  one week ,It drive me crazy ...

 

UCF

 


INST "*GTX_DUAL_1000X_inst/GTX_1000X/tile0_rocketio_wrapper_gtx_i/gtx_dual_i" LOC = "GTX_DUAL_X0Y4";

net "*/hrst*" TIG;

# EMAC0 RX Client Clock
NET "*/RxClientClk_0" TNM_NET = "clk_client_rx0";
TIMEGRP "gmii_client_clk_rx0" = "clk_client_rx0";
TIMESPEC "TS_gmii_client_clk_rx0" = PERIOD "gmii_client_clk_rx0" 7500 ps HIGH 50 %;

NET "*Hard_Ethernet_MAC*/LlinkTemac0_CLK" TNM_NET = "LLCLK0"; #name of signal connected to TEMAC LlinkTemac0_CLK input
NET "*Hard_Ethernet_MAC*/SPLB_Clk" TNM_NET = "PLBCLK"; #name of signal connected to TEMAC SPLB_Clk input

TIMESPEC TS_PLB_2_LL0 = FROM PLBCLK TO LLCLK0 8000 ps DATAPATHONLY; #constant value based on LocalLink clock
TIMESPEC TS_LL0_2_PLB = FROM LLCLK0 TO PLBCLK 8000 ps DATAPATHONLY; #varies based on period of PLB clock

TIMESPEC "TS_LL_CLK0_2_RX_CLIENT_CLK0" = FROM LLCLK0 TO clk_client_rx0 8000 ps DATAPATHONLY; #constant value based on Ethernet clock
TIMESPEC "TS_RX_CLIENT_CLK0_2_LL_CLK0" = FROM clk_client_rx0 TO LLCLK0 8000 ps DATAPATHONLY; #varies based on period of LocalLink clock

#-----------------------------------------------------------

# EMAC0 Fabric Rx Elastic Buffer Timing Constraints: -

#-----------------------------------------------------------

NET "*GTX_DUAL_1000X_inst?RXRECCLK_0_BUFR" TNM_NET = "clk_rec_clk0";
TIMEGRP "sgmii_client_rec_clk0" = "clk_rec_clk0";
TIMESPEC "TS_sgmii_rec_clk0" = PERIOD "sgmii_client_rec_clk0" 7700 ps HIGH 50 %;

# Control Gray Code delay and skew
NET "*GTX_DUAL_1000X_inst?rx_elastic_buffer_inst_0?wr_addr_gray<?>" MAXDELAY = 6 ns;

# Reduce clock period to allow 3 ns for metastability settling time
INST "*GTX_DUAL_1000X_inst?rx_elastic_buffer_inst_0?rd_wr_addr_gray*" TNM = "rx_graycode_0";
INST "*GTX_DUAL_1000X_inst?rx_elastic_buffer_inst_0?rd_occupancy*" TNM = "rx_binary_0";
TIMESPEC "ts_rx_buf_meta_protect_0" = FROM "rx_graycode_0" TO "rx_binary_0" 5 ns;

# The following constraint must be uncommented when targeting a SGMII or 1000Base-X system
# with a -1 speed grade Virtex-5 device
#
#INST "*clk62_5_dcm" DLL_FREQUENCY_MODE = HIGH;
net "*/hrst*" TIG;
###net "*/V5HARD_SYS.I_TEMAC/speed_vector_0_i*" TIG;

==================================================================================

 

MHS

 

PARAMETER VERSION = 2.1.0


PORT fpga_0_RS232_Uart_1_RX_pin = fpga_0_RS232_Uart_1_RX_pin, DIR = I
PORT fpga_0_RS232_Uart_1_TX_pin = fpga_0_RS232_Uart_1_TX_pin, DIR = O
PORT fpga_0_SRAM_Mem_A_pin = fpga_0_SRAM_Mem_A_pin_vslice_7_30_concat, DIR = O, VEC = [7:30]
PORT fpga_0_SRAM_Mem_CEN_pin = fpga_0_SRAM_Mem_CEN_pin, DIR = O
PORT fpga_0_SRAM_Mem_OEN_pin = fpga_0_SRAM_Mem_OEN_pin, DIR = O
PORT fpga_0_SRAM_Mem_WEN_pin = fpga_0_SRAM_Mem_WEN_pin, DIR = O
PORT fpga_0_SRAM_Mem_BEN_pin = fpga_0_SRAM_Mem_BEN_pin, DIR = O, VEC = [0:3]
PORT fpga_0_SRAM_Mem_ADV_LDN_pin = fpga_0_SRAM_Mem_ADV_LDN_pin, DIR = O
PORT fpga_0_SRAM_Mem_DQ_pin = fpga_0_SRAM_Mem_DQ_pin, DIR = IO, VEC = [0:31]
PORT fpga_0_SRAM_ZBT_CLK_OUT_pin = SRAM_CLK_OUT_s, DIR = O
PORT fpga_0_SRAM_ZBT_CLK_FB_pin = SRAM_CLK_FB_s, DIR = I, SIGIS = CLK, CLK_FREQ = 125000000
PORT fpga_0_DDR2_SDRAM_DDR2_Clk_pin = fpga_0_DDR2_SDRAM_DDR2_Clk_pin, DIR = O, VEC = [1:0]
PORT fpga_0_DDR2_SDRAM_DDR2_Clk_n_pin = fpga_0_DDR2_SDRAM_DDR2_Clk_n_pin, DIR = O, VEC = [1:0]
PORT fpga_0_DDR2_SDRAM_DDR2_CE_pin = fpga_0_DDR2_SDRAM_DDR2_CE_pin, DIR = O
PORT fpga_0_DDR2_SDRAM_DDR2_CS_n_pin = fpga_0_DDR2_SDRAM_DDR2_CS_n_pin, DIR = O
PORT fpga_0_DDR2_SDRAM_DDR2_ODT_pin = fpga_0_DDR2_SDRAM_DDR2_ODT_pin, DIR = O, VEC = [1:0]
PORT fpga_0_DDR2_SDRAM_DDR2_RAS_n_pin = fpga_0_DDR2_SDRAM_DDR2_RAS_n_pin, DIR = O
PORT fpga_0_DDR2_SDRAM_DDR2_CAS_n_pin = fpga_0_DDR2_SDRAM_DDR2_CAS_n_pin, DIR = O
PORT fpga_0_DDR2_SDRAM_DDR2_WE_n_pin = fpga_0_DDR2_SDRAM_DDR2_WE_n_pin, DIR = O
PORT fpga_0_DDR2_SDRAM_DDR2_BankAddr_pin = fpga_0_DDR2_SDRAM_DDR2_BankAddr_pin, DIR = O, VEC = [1:0]
PORT fpga_0_DDR2_SDRAM_DDR2_Addr_pin = fpga_0_DDR2_SDRAM_DDR2_Addr_pin, DIR = O, VEC = [12:0]
PORT fpga_0_DDR2_SDRAM_DDR2_DQ_pin = fpga_0_DDR2_SDRAM_DDR2_DQ_pin, DIR = IO, VEC = [63:0]
PORT fpga_0_DDR2_SDRAM_DDR2_DM_pin = fpga_0_DDR2_SDRAM_DDR2_DM_pin, DIR = O, VEC = [7:0]
PORT fpga_0_DDR2_SDRAM_DDR2_DQS_pin = fpga_0_DDR2_SDRAM_DDR2_DQS_pin, DIR = IO, VEC = [7:0]
PORT fpga_0_DDR2_SDRAM_DDR2_DQS_n_pin = fpga_0_DDR2_SDRAM_DDR2_DQS_n_pin, DIR = IO, VEC = [7:0]
PORT fpga_0_clk_1_sys_clk_pin = dcm_clk_s, DIR = I, SIGIS = CLK, CLK_FREQ = 100000000
PORT fpga_0_rst_1_sys_rst_pin = sys_rst_s, DIR = I, SIGIS = RST, RST_POLARITY = 0
PORT fpga_0_Hard_Ethernet_MAC_TemacPhy_RST_n_pin = fpga_0_Hard_Ethernet_MAC_TemacPhy_RST_n_pin, DIR = O
PORT fpga_0_Hard_Ethernet_MAC_MDC_0_pin = fpga_0_Hard_Ethernet_MAC_MDC_0_pin, DIR = O
PORT fpga_0_Hard_Ethernet_MAC_MDIO_0_pin = fpga_0_Hard_Ethernet_MAC_MDIO_0_pin, DIR = IO
PORT fpga_0_Hard_Ethernet_MAC_PHY_MII_INT_pin = fpga_0_Hard_Ethernet_MAC_PHY_MII_INT_pin, DIR = I, SIGIS = INTERRUPT, SENSITIVITY = LEVEL_LOW, INTERRUPT_PRIORITY = MEDIUM
PORT Hard_Ethernet_MAC_MGTCLK_P_pin = Hard_Ethernet_MAC_MGTCLK_P, DIR = I
PORT Hard_Ethernet_MAC_MGTCLK_N_pin = Hard_Ethernet_MAC_MGTCLK_N, DIR = I
PORT Hard_Ethernet_MAC_TXP_0_pin = Hard_Ethernet_MAC_TXP_0, DIR = O
PORT Hard_Ethernet_MAC_TXN_0_pin = Hard_Ethernet_MAC_TXN_0, DIR = O
PORT Hard_Ethernet_MAC_RXP_0_pin = Hard_Ethernet_MAC_RXP_0, DIR = I
PORT Hard_Ethernet_MAC_RXN_0_pin = Hard_Ethernet_MAC_RXN_0, DIR = I


BEGIN microblaze
PARAMETER INSTANCE = microblaze_0
PARAMETER C_USE_BARREL = 1
PARAMETER C_DEBUG_ENABLED = 1
PARAMETER HW_VER = 8.00.b
BUS_INTERFACE DLMB = dlmb
BUS_INTERFACE ILMB = ilmb
BUS_INTERFACE DPLB = mb_plb
BUS_INTERFACE IPLB = mb_plb
BUS_INTERFACE DEBUG = microblaze_0_mdm_bus
PORT MB_RESET = mb_reset
PORT INTERRUPT = microblaze_0_Interrupt
END

BEGIN plb_v46
PARAMETER INSTANCE = mb_plb
PARAMETER HW_VER = 1.05.a
PORT PLB_Clk = clk_125_0000MHzPLL0
PORT SYS_Rst = sys_bus_reset
END

BEGIN lmb_v10
PARAMETER INSTANCE = ilmb
PARAMETER HW_VER = 1.00.a
PORT LMB_Clk = clk_125_0000MHzPLL0
PORT SYS_Rst = sys_bus_reset
END

BEGIN lmb_v10
PARAMETER INSTANCE = dlmb
PARAMETER HW_VER = 1.00.a
PORT LMB_Clk = clk_125_0000MHzPLL0
PORT SYS_Rst = sys_bus_reset
END

BEGIN lmb_bram_if_cntlr
PARAMETER INSTANCE = dlmb_cntlr
PARAMETER HW_VER = 2.10.b
PARAMETER C_BASEADDR = 0x00000000
PARAMETER C_HIGHADDR = 0x0000ffff
BUS_INTERFACE SLMB = dlmb
BUS_INTERFACE BRAM_PORT = dlmb_port
END

BEGIN lmb_bram_if_cntlr
PARAMETER INSTANCE = ilmb_cntlr
PARAMETER HW_VER = 2.10.b
PARAMETER C_BASEADDR = 0x00000000
PARAMETER C_HIGHADDR = 0x0000ffff
BUS_INTERFACE SLMB = ilmb
BUS_INTERFACE BRAM_PORT = ilmb_port
END

BEGIN bram_block
PARAMETER INSTANCE = lmb_bram
PARAMETER HW_VER = 1.00.a
BUS_INTERFACE PORTA = ilmb_port
BUS_INTERFACE PORTB = dlmb_port
END

BEGIN xps_uartlite
PARAMETER INSTANCE = RS232_Uart_1
PARAMETER C_BAUDRATE = 9600
PARAMETER C_DATA_BITS = 8
PARAMETER C_USE_PARITY = 0
PARAMETER C_ODD_PARITY = 0
PARAMETER HW_VER = 1.01.a
PARAMETER C_BASEADDR = 0x84000000
PARAMETER C_HIGHADDR = 0x8400ffff
BUS_INTERFACE SPLB = mb_plb
PORT RX = fpga_0_RS232_Uart_1_RX_pin
PORT TX = fpga_0_RS232_Uart_1_TX_pin
END

BEGIN xps_mch_emc
PARAMETER INSTANCE = SRAM
PARAMETER C_NUM_BANKS_MEM = 1
PARAMETER C_NUM_CHANNELS = 0
PARAMETER C_MEM0_WIDTH = 32
PARAMETER C_MAX_MEM_WIDTH = 32
PARAMETER C_INCLUDE_DATAWIDTH_MATCHING_0 = 0
PARAMETER C_SYNCH_MEM_0 = 1
PARAMETER C_TCEDV_PS_MEM_0 = 0
PARAMETER C_TAVDV_PS_MEM_0 = 0
PARAMETER C_THZCE_PS_MEM_0 = 0
PARAMETER C_THZOE_PS_MEM_0 = 0
PARAMETER C_TWC_PS_MEM_0 = 0
PARAMETER C_TWP_PS_MEM_0 = 0
PARAMETER C_TLZWE_PS_MEM_0 = 0
PARAMETER HW_VER = 3.01.a
PARAMETER C_MEM0_BASEADDR = 0x8a400000
PARAMETER C_MEM0_HIGHADDR = 0x8a4fffff
BUS_INTERFACE SPLB = mb_plb
PORT RdClk = clk_125_0000MHzPLL0
PORT Mem_A = 0b0000000 & fpga_0_SRAM_Mem_A_pin_vslice_7_30_concat & 0b0
PORT Mem_CEN = fpga_0_SRAM_Mem_CEN_pin
PORT Mem_OEN = fpga_0_SRAM_Mem_OEN_pin
PORT Mem_WEN = fpga_0_SRAM_Mem_WEN_pin
PORT Mem_BEN = fpga_0_SRAM_Mem_BEN_pin
PORT Mem_ADV_LDN = fpga_0_SRAM_Mem_ADV_LDN_pin
PORT Mem_DQ = fpga_0_SRAM_Mem_DQ_pin
END

BEGIN mpmc
PARAMETER INSTANCE = DDR2_SDRAM
PARAMETER C_NUM_PORTS = 2
PARAMETER C_NUM_IDELAYCTRL = 3
PARAMETER C_IDELAYCTRL_LOC = IDELAYCTRL_X0Y6-IDELAYCTRL_X0Y2-IDELAYCTRL_X0Y1
PARAMETER C_MEM_PARTNO = mt4htf3264h-53e
PARAMETER C_MEM_ODT_TYPE = 1
PARAMETER C_MEM_CLK_WIDTH = 2
PARAMETER C_MEM_ODT_WIDTH = 2
PARAMETER C_MEM_CE_WIDTH = 1
PARAMETER C_MEM_CS_N_WIDTH = 1
PARAMETER C_MEM_DATA_WIDTH = 64
PARAMETER C_DDR2_DQSN_ENABLE = 1
PARAMETER C_PIM0_BASETYPE = 2
PARAMETER HW_VER = 6.02.a
PARAMETER C_SDMA1_PI2LL_CLK_RATIO = 1
PARAMETER C_PIM1_BASETYPE = 3
PARAMETER C_MPMC_BASEADDR = 0x90000000
PARAMETER C_MPMC_HIGHADDR = 0x9fffffff
PARAMETER C_SDMA_CTRL_BASEADDR = 0x84600000
PARAMETER C_SDMA_CTRL_HIGHADDR = 0x8460ffff
BUS_INTERFACE SPLB0 = mb_plb
BUS_INTERFACE SDMA_CTRL1 = mb_plb
BUS_INTERFACE SDMA_LL1 = Hard_Ethernet_MAC_LLINK0
PORT MPMC_Clk0 = clk_125_0000MHzPLL0
PORT MPMC_Clk0_DIV2 = clk_62_5000MHzPLL0
PORT MPMC_Clk90 = clk_125_0000MHz90PLL0
PORT MPMC_Clk_200MHz = clk_200_0000MHz
PORT MPMC_Rst = sys_periph_reset
PORT DDR2_Clk = fpga_0_DDR2_SDRAM_DDR2_Clk_pin
PORT DDR2_Clk_n = fpga_0_DDR2_SDRAM_DDR2_Clk_n_pin
PORT DDR2_CE = fpga_0_DDR2_SDRAM_DDR2_CE_pin
PORT DDR2_CS_n = fpga_0_DDR2_SDRAM_DDR2_CS_n_pin
PORT DDR2_ODT = fpga_0_DDR2_SDRAM_DDR2_ODT_pin
PORT DDR2_RAS_n = fpga_0_DDR2_SDRAM_DDR2_RAS_n_pin
PORT DDR2_CAS_n = fpga_0_DDR2_SDRAM_DDR2_CAS_n_pin
PORT DDR2_WE_n = fpga_0_DDR2_SDRAM_DDR2_WE_n_pin
PORT DDR2_BankAddr = fpga_0_DDR2_SDRAM_DDR2_BankAddr_pin
PORT DDR2_Addr = fpga_0_DDR2_SDRAM_DDR2_Addr_pin
PORT DDR2_DQ = fpga_0_DDR2_SDRAM_DDR2_DQ_pin
PORT DDR2_DM = fpga_0_DDR2_SDRAM_DDR2_DM_pin
PORT DDR2_DQS = fpga_0_DDR2_SDRAM_DDR2_DQS_pin
PORT DDR2_DQS_n = fpga_0_DDR2_SDRAM_DDR2_DQS_n_pin
PORT SDMA1_Clk = clk_125_0000MHzPLL0
PORT SDMA1_Rx_IntOut = DDR2_SDRAM_SDMA1_Rx_IntOut
PORT SDMA1_Tx_IntOut = DDR2_SDRAM_SDMA1_Tx_IntOut
END

BEGIN xps_timer
PARAMETER INSTANCE = xps_timer_0
PARAMETER C_COUNT_WIDTH = 32
PARAMETER C_ONE_TIMER_ONLY = 0
PARAMETER HW_VER = 1.02.a
PARAMETER C_BASEADDR = 0x83c00000
PARAMETER C_HIGHADDR = 0x83c0ffff
BUS_INTERFACE SPLB = mb_plb
PORT Interrupt = xps_timer_0_Interrupt
END

BEGIN clock_generator
PARAMETER INSTANCE = clock_generator_0
PARAMETER C_CLKIN_FREQ = 100000000
PARAMETER C_CLKOUT0_FREQ = 125000000
PARAMETER C_CLKOUT0_PHASE = 90
PARAMETER C_CLKOUT0_GROUP = PLL0
PARAMETER C_CLKOUT0_BUF = TRUE
PARAMETER C_CLKOUT1_FREQ = 125000000
PARAMETER C_CLKOUT1_PHASE = 0
PARAMETER C_CLKOUT1_GROUP = PLL0
PARAMETER C_CLKOUT1_BUF = TRUE
PARAMETER C_CLKOUT2_FREQ = 200000000
PARAMETER C_CLKOUT2_PHASE = 0
PARAMETER C_CLKOUT2_GROUP = NONE
PARAMETER C_CLKOUT2_BUF = TRUE
PARAMETER C_CLKOUT3_FREQ = 62500000
PARAMETER C_CLKOUT3_PHASE = 0
PARAMETER C_CLKOUT3_GROUP = PLL0
PARAMETER C_CLKOUT3_BUF = TRUE
PARAMETER C_CLKFBIN_FREQ = 125000000
PARAMETER C_CLKFBOUT_FREQ = 125000000
PARAMETER C_CLKFBOUT_BUF = TRUE
PARAMETER C_EXT_RESET_HIGH = 0
PARAMETER HW_VER = 4.01.a
PORT CLKIN = dcm_clk_s
PORT CLKOUT0 = clk_125_0000MHz90PLL0
PORT CLKOUT1 = clk_125_0000MHzPLL0
PORT CLKOUT2 = clk_200_0000MHz
PORT CLKOUT3 = clk_62_5000MHzPLL0
PORT CLKFBIN = SRAM_CLK_FB_s
PORT CLKFBOUT = SRAM_CLK_OUT_s
PORT RST = sys_rst_s
PORT LOCKED = Dcm_all_locked
END

BEGIN mdm
PARAMETER INSTANCE = mdm_0
PARAMETER C_MB_DBG_PORTS = 1
PARAMETER C_USE_UART = 1
PARAMETER HW_VER = 2.00.a
PARAMETER C_BASEADDR = 0x84400000
PARAMETER C_HIGHADDR = 0x8440ffff
BUS_INTERFACE SPLB = mb_plb
BUS_INTERFACE MBDEBUG_0 = microblaze_0_mdm_bus
PORT Debug_SYS_Rst = Debug_SYS_Rst
END

BEGIN proc_sys_reset
PARAMETER INSTANCE = proc_sys_reset_0
PARAMETER C_EXT_RESET_HIGH = 0
PARAMETER HW_VER = 3.00.a
PORT Slowest_sync_clk = clk_125_0000MHzPLL0
PORT Ext_Reset_In = sys_rst_s
PORT MB_Debug_Sys_Rst = Debug_SYS_Rst
PORT Dcm_locked = Dcm_all_locked
PORT MB_Reset = mb_reset
PORT Bus_Struct_Reset = sys_bus_reset
PORT Peripheral_Reset = sys_periph_reset
END

BEGIN xps_intc
PARAMETER INSTANCE = xps_intc_0
PARAMETER HW_VER = 2.01.a
PARAMETER C_BASEADDR = 0x81800000
PARAMETER C_HIGHADDR = 0x8180ffff
BUS_INTERFACE SPLB = mb_plb
PORT Intr = Hard_Ethernet_MAC_TemacIntc0_Irpt & xps_timer_0_Interrupt & DDR2_SDRAM_SDMA1_Rx_IntOut & DDR2_SDRAM_SDMA1_Tx_IntOut & fpga_0_Hard_Ethernet_MAC_PHY_MII_INT_pin
PORT Irq = microblaze_0_Interrupt
END

BEGIN xps_ll_temac
PARAMETER INSTANCE = Hard_Ethernet_MAC
PARAMETER C_NUM_IDELAYCTRL = 2
PARAMETER C_IDELAYCTRL_LOC = IDELAYCTRL_X0Y4-IDELAYCTRL_X1Y5
PARAMETER C_PHY_TYPE = 4
PARAMETER C_TEMAC1_ENABLED = 0
PARAMETER C_BUS2CORE_CLK_RATIO = 1
PARAMETER C_TEMAC_TYPE = 0
PARAMETER C_TEMAC0_PHYADDR = 0b00001
PARAMETER HW_VER = 2.03.a
PARAMETER C_TEMAC0_TXFIFO = 32768
PARAMETER C_TEMAC0_RXFIFO = 32768
PARAMETER C_BASEADDR = 0x87580000
PARAMETER C_HIGHADDR = 0x875fffff
BUS_INTERFACE SPLB = mb_plb
BUS_INTERFACE LLINK0 = Hard_Ethernet_MAC_LLINK0
PORT TemacIntc0_Irpt = Hard_Ethernet_MAC_TemacIntc0_Irpt
PORT TemacPhy_RST_n = fpga_0_Hard_Ethernet_MAC_TemacPhy_RST_n_pin
PORT LlinkTemac0_CLK = clk_125_0000MHzPLL0
PORT MDC_0 = fpga_0_Hard_Ethernet_MAC_MDC_0_pin
PORT MDIO_0 = fpga_0_Hard_Ethernet_MAC_MDIO_0_pin
PORT MGTCLK_P = Hard_Ethernet_MAC_MGTCLK_P
PORT MGTCLK_N = Hard_Ethernet_MAC_MGTCLK_N
PORT TXP_0 = Hard_Ethernet_MAC_TXP_0
PORT TXN_0 = Hard_Ethernet_MAC_TXN_0
PORT RXP_0 = Hard_Ethernet_MAC_RXP_0
PORT RXN_0 = Hard_Ethernet_MAC_RXN_0
END

 

Thanks ,I really need help~

 

0 Kudos
6 Replies
5,159 Views
Registered: ‎12-23-2011

Re: can't telnet to ML507 (I used TEMAC and chose SGMII )

As you said, you should check your ucf as per schematic of ML507.

If that is ok you can check whether signals are coming out to RJ45 connector on osciloscope.

And if that is also ok, I will suggest you simulate your code for RX-TX short of TEMAC externally and see whether it is working fine.

0 Kudos
Scholar golson
Scholar
5,151 Views
Registered: ‎04-07-2008

Re: can't telnet to ML507 (I used TEMAC and chose SGMII )

Were you able to ping the board.  If you are trying to telnet to the board are you running eith a operating system.

0 Kudos
Voyager
Voyager
5,140 Views
Registered: ‎02-10-2012

Re: can't telnet to ML507 (I used TEMAC and chose SGMII )

Some important settings u must take care of before the echo server can work perfectly. If u say u have done all the imp steps in adding the ip and designing the hardware then it must be a network issue.

 

1) First and foremost make sure the IP set on the board and the IP used by your computer are in the same range. As in if ur computer ip is suppose 192.168.64.100 make sure your board ip is some where around 192.168.64.xxx

 

2) Try to ping the board. If it pings then half your problems are solved. 

 

3) If it dosent then u will have to use the network debugger software called wire shark to see if u are getting the ARP requests.

 

 

0 Kudos
Visitor ctbctb
Visitor
5,127 Views
Registered: ‎04-08-2012

Re: can't telnet to ML507 (I used TEMAC and chose SGMII )

I tried ,but failed ,I run a standalone OS on the board

 
0 Kudos
Visitor ctbctb
Visitor
5,126 Views
Registered: ‎04-08-2012

Re: can't telnet to ML507 (I used TEMAC and chose SGMII )

the UCF is downloaded form the Xilinx website ,it's may be OK,but I'm not sure , I think next step I could do as you suggest , check it step by step ,thx....
0 Kudos
Visitor ctbctb
Visitor
5,125 Views
Registered: ‎04-08-2012

Re: can't telnet to ML507 (I used TEMAC and chose SGMII )

i have tried the 1)and 2), failed , I think the third suggestion is a good suggestion , i'll try , I hope It can help me find something important ....thanks
0 Kudos