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Visitor vibhuthk
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1,509 Views
Registered: ‎06-06-2014

chow to create fsl ports in a module in verilog??

i am trying to make module and in this i want both master fsl as input and slave fsl as output, can anyone please tell what architecture should i use to declare these input output ports in verilog.
i just want that these ports become compatible to microblaze.

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