04-14-2012 04:12 AM
I am trying to write my custom ip which contains a read packet fifo. my custom ip has an external clock and this clock should control the read fifo. so for testing version of my code I generate an example clock and I conencted it to rdfifo_top in my top module. but it doesnt work. with ipif_Bus2IP_Clk I can read my data from read fifo (which I write them) but with this clock the fifo does not work.
please help me
-- instantiate rdpfifo_top
RDPFIFO_TOP_I : entity rdpfifo_v4_02_a.rdpfifo_top
C_OPB_PROTOCOL => false,
C_MIR_ENABLE => false,
C_BLOCK_ID => 0,
C_NUM_REG_CE => RFF_NUM_REG_CE,
C_FIFO_DEPTH_LOG2X => RFF_FIFO_DEPTH_LOG2X,
C_FIFO_WIDTH => IPIF_SLV_DWIDTH,
C_INCLUDE_PACKET_MODE => RFF_INCLUDE_PACKET_MODE,
C_INCLUDE_VACANCY => RFF_INCLUDE_VACANCY,
C_SUPPORT_BURST => RFF_SUPPORT_BURST,
C_IPIF_DBUS_WIDTH => IPIF_SLV_DWIDTH,
C_FAMILY => C_FAMILY
Bus_rst => FIFO_RST, --ipif_Bus2IP_Reset,
Bus_Clk => ADC_CLK_FOR_TEST, --ipif_Bus2IP_Clk,
Bus_Burst => '0',
Bus_BE => ipif_Bus2IP_BE,
Bus2FIFO_Reg_RdCE => ipif_Bus2IP_RdCE(RFF_REG_CE_INDEX to RFF_REG_CE_INDEX+RFF_NUM_REG_CE-1),
Bus2FIFO_Data_RdCE => ipif_Bus2IP_RdCE(RFF_DAT_CE_INDEX),
Bus2FIFO_Reg_WrCE => ipif_Bus2IP_WrCE(RFF_REG_CE_INDEX to RFF_REG_CE_INDEX+RFF_NUM_REG_CE-1),
Bus2FIFO_Data_WrCE => ipif_Bus2IP_WrCE(RFF_DAT_CE_INDEX),
Bus_DBus => ipif_Bus2IP_Data,
Rdfifo_Pop => '0',
IP2RFIFO_WrReq => user_IP2RFIFO_WrReq,
IP2RFIFO_WrMark => user_IP2RFIFO_WrMark,
IP2RFIFO_WrRestore => user_IP2RFIFO_WrRestore,
IP2RFIFO_WrRelease => user_IP2RFIFO_WrRelease,
IP2RFIFO_Data => user_IP2RFIFO_Data,
RFIFO2IP_WrAck => rff_RFIFO2IP_WrAck,
RFIFO2IP_AlmostFull => rff_RFIFO2IP_AlmostFull,
RFIFO2IP_Full => rff_RFIFO2IP_Full,
RFIFO2IP_Vacancy => rff_RFIFO2IP_Vacancy,
RFIFO2DMA_AlmostEmpty => open,
RFIFO2DMA_Empty => open,
RFIFO2DMA_Occupancy => open,
FIFO2IRPT_DeadLock => open,
FIFO2Bus_DBus => rff_IP2Bus_Data,
FIFO2Bus_WrAck => rff_IP2Bus_WrAck,
FIFO2Bus_RdAck => rff_IP2Bus_RdAck,
FIFO2Bus_Error => rff_IP2Bus_Error,
FIFO2Bus_Retry => open,
FIFO2Bus_ToutSup => open
--------------------------- TEST ADC_CLK and PRF signal-------------------------
ADC_CLK_GEN : process( ipif_Bus2IP_Clk , ipif_Bus2IP_Reset ) is
if ( ipif_Bus2IP_Clk'event and ipif_Bus2IP_Clk = '1' ) then
if ( ipif_Bus2IP_Reset = '1' ) then
cnt <= "00";
cnt <= cnt + '1';
if cnt < "10" then
ADC_CLK_FOR_TEST <= '1';
ADC_CLK_FOR_TEST <= '0';
end process ADC_CLK_GEN;
04-14-2012 12:36 PM - edited 04-14-2012 12:37 PM
but it doesnt work
What doesn't work? Do you get any data out of the FIFO? Do you have synthesis problems? How are your FIFO enables related to ADC_CLK_FOR_TEST? What does your simulation show? Can you post some waveforms and highlight the "not working" part?
I don't fully understand the part of code you have written but you seem to generating a SIGNAL to be used as a CLOCK. If you have instantiated an IP FIFO (i.e. from coregen), it might not like this. What happens if you generate the ADC_CLK_FOR_TEST clock frequency you want from the clock_generator module in the system instead of your "logic clock"?
In short, you need to describe your problem more precisely.
04-14-2012 09:49 PM
thanks for your quick reply.
when I am using ipif_Bus2IP_Clk for read fifo clock, I can read my data from fifo but when I connect ADC_CLK_FOR_TEST to read fifo clock I read nothing.
I dont have any simulation result because I dont know how to do that ( now I am trying to learn) but I do connect one of clock generator outputs to ADC_CLK_FOR_TEST (as you said) but it doesnt work neither.
what do you suggest me to do?
04-15-2012 11:28 AM
what do you suggest me to do?
1. Don't use logic generated "clock" to drive the FIFO
2. Ensure that your FIFO read control signals are synchronised to your read clock, including the PLB read acknowledge
3. Simulate. Take the IP into Project Navigator and simulate as a standalone item if it is easier than trying to simulate the whole EDK design
I cannot stress how important it is to simulate. You positively MUST learn to do this. Without some visual aid to determine what is going on (even if only theoretically), everything else is just guess work.
04-15-2012 10:44 PM
I am trying to use ISim to simulate my IP but I dont know how to take my ip to ISE. so is it enough to use ISim or I need to use BFM simulation too?
could you help me by some documents about ISim. I am getting confused about these things :(
04-15-2012 11:19 PM
I don't believe you need to worry about BFM simulation.
I'm afraid that I cannot help you directly with ISim, as I have never used it. I use ModelSim, however, the principles should be the same. You need to set up stimuli for your IP and then observe the necessary signals over time. There must be a User Guide for ISim that can help you do this.
When I wrote "take your IP to Project Navigator" I meant start a whole new project in PN that only deals with your IP at that new project's top level. You should be able to invoke the simulator of your choice directly from PN in this case. I find this makes it easier to see the IP in focus rather than bundled with the rest of the EDK project, which can be confusing.
You haven't, as yet, addressed my queries regarding the synchronisation of your FIFO read control signals to your read clock. If you are changing read clock frequency, your read control signals MUST be related to this clock - your previous code snippet suggests to me that they are still synchronised to the Bus2IP_Clock, so you may be getting data out of the FIFO at times you do not want or expect.
I trust these comments make sense to you.
04-16-2012 11:07 PM
now I am starting to work with BFM and I have a lot of questions :). I will post a new message about it.
if I can fix my read fifo I will tell you what I did.