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Explorer
Explorer
3,660 Views
Registered: ‎12-29-2008

design working on FPGA but giving hold violations on timing simulation????

Hi,

I have a design which is working at 100mhz on virtex4(ml403) device, but when i do post routed static timing then reports are showing that there  is timing violation .. How could it be possible ?? i am confused , am i doing any mistake.. please guide me ..

 

thanks in advance,

regards,

Krishna Kishore 

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2 Replies
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Scholar
Scholar
3,643 Views
Registered: ‎04-07-2008

You may have timing violations that do not fail the operation of the design.  that is why you may need to timing ignore signals failing timing

but are not affecting the fpga design operation at all.

 

Have you used the timing analyzer tool to find the signals failing timing?

 

 

 

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Xilinx Employee
Xilinx Employee
3,639 Views
Registered: ‎08-13-2007

As indicated, you should run trce/Timing Analyzer first to make sure the design meets timing before simulating with these delays.

 

It is also possible that a design could work in real-life when it fails timing - typically because of margin in PVT (process, voltage, or temperature). But that certainly doesn't mean it is a good practice. ;)

 

You may also find this useful:

http://www.xilinx.com/support/answers/21367.htm (10.1 Timing - How do I fix a Hold Time Violation?)

 

bt

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