03-08-2017 11:23 AM
I am working on a project on Zynq Ultrascale+ MPSoc using vivado.2016.3. I have created my block design in vivado and software program in SDK. The software is working fine with SDK through Jtag. Right now, I want to create communication interface between host (PC) and fpga through Matlab/USB_JTAG(For example, I want to read/write register to fpga in matlab). How to implement this kind of interface? Are there any example design?
Thank you in advance!
03-08-2017 12:02 PM
If you use a xilinx board, jtag port must be dual purpose.Both programming and UART. If you don't mean programming,you can open simple Serial Port on Matlab. You can use AXILite UART or Zyq drivers on PS side to communicate with PC. Of course you should use an application code which registers want to read/write.
03-08-2017 02:54 PM
What I want to do is downloading the system.bit file generated from vivado and application.elf file from SDK to zynq board through matlab.
In SDK, we have command 'source' to load the psu_init, rst to reset fpga and dow command to download images, I am wondering if matlab has equivalent drivers to do the same thing through the jtag.
03-09-2017 11:42 AM
Any clues about how to use matlab to download the fpga image generated from vivado (system.bit) to the zynq board?
03-10-2017 08:46 AM
I found in Altera, they provide Matlab API, SystemConsole, to allow matlab to establish Jtag connection and control fpga. I am wondering if XIlinx has similar API functions for matlab.
The second thought is, In vivado hw debugger, when we connect the board using tcl command 'connect_hw_server' in tcl console, I believe the console indeed are calling some low level driver's API funcion in background to establish connection with Itag, and the whole process is not visible. Is that possible to find out what it calls while we type those tcl commands, and the location of those low level functions?
04-02-2017 10:58 PM
You can check Hardware in the Loop(HWIL) concept in Matlab.
It works HDL Coder generated .bit fle. You must test it also with your custom .bit file.
05-29-2017 10:46 AM
05-30-2017 01:15 AM
I don't really understand why you are trying to control Xilinx SDK from matlab if you are not generating code at all from Matlab by itself...
Matlab/Simulink Embedded Coder (SW) and HDL coder (HW) can be used to generate code and the third party support packages to program those applications/bitstreams into your target. Currently as far as I know they don't provide a SP for ZynqMP as they do for Zynq-7000.
Using this third party package definitively allows to control Xilinx tools, but commonly this is commonly used for code generated within matlab rather than in SDK/Vivado tools.